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inv_syn_cegar.h
1 // ---Hongce Zhang
3 
4 #ifndef ILANG_VTARGET_OUT_INV_SYN_CEGAR_H__
5 #define ILANG_VTARGET_OUT_INV_SYN_CEGAR_H__
6 
7 #include <ilang/config.h>
8 #ifdef INVSYN_INTERFACE
9 
10 #include <ilang/smt-inout/yosys_smt_parser.h>
11 #include <ilang/vtarget-out/design_stat.h>
12 #include <ilang/vtarget-out/vtarget_gen.h>
13 
14 #include <memory>
15 #include <string>
16 
17 namespace ilang {
18 
20 class InvariantSynthesizerCegar {
21 
22 public:
23  // -------------------- TYPES ------------------ //
25  using verify_backend_selector = VlgVerifTgtGenBase::backend_selector;
27  using vtg_config_t = VlgVerifTgtGenBase::vtg_config_t;
29  using synthesis_backend_selector =
34  typedef enum { NEXT_V, V_RES, NEXT_S, S_RES, DONE, FAILED } cegar_status;
36  using advanced_parameters_t = VlgVerifTgtGenBase::advanced_parameters_t;
38  enum _inv_check_res_t { INV_PROVED, INV_INVALID, INV_UNKNOWN };
40  typedef std::map<std::string, int> additional_width_info_t;
41 
42 public:
43  // -------------------- CONSTRUCTOR ------------------ //
45  InvariantSynthesizerCegar(
46  const std::vector<std::string>& implementation_include_path,
47  const std::vector<std::string>& implementation_srcs,
48  const std::string& implementation_top_module,
49  const std::string& refinement_variable_mapping,
50  const std::string& refinement_conditions, const std::string& output_path,
51  const InstrLvlAbsPtr& ila_ptr, verify_backend_selector vbackend,
52  synthesis_backend_selector sbackend,
53  const vtg_config_t& vtg_config = vtg_config_t(),
54  const VerilogGenerator::VlgGenConfig& config =
57  InvariantSynthesizerCegar(const InvariantSynthesizerCegar&) = delete;
59  InvariantSynthesizerCegar&
60  operator=(const InvariantSynthesizerCegar&) = delete;
61 
62 public:
63  // -------------------- HELPERs ------------------ //
64  // to do things separately, you can provide the run function your self
65  // or even do it step by step
67  void GenerateVerificationTarget();
69  void GenerateVerificationTarget(const std::vector<std::string>& invs);
71  void GenerateInvariantVerificationTarget();
73  void ExtractVerificationResult(bool autodet = true, bool pass = true,
74  const std::string& res_file = "",
75  const std::string& mod_inst_name = "");
76 
78  void GenerateTargetAndExtractSmt();
80  unsigned QueryRtlStateWidth(const std::string& name) const;
81 
83  void CexGeneralizeRemoveStates(const std::vector<std::string>&);
85  void GenerateSynthesisTarget();
87  void ExtractSynthesisResult(bool autodet = true, bool reachable = true,
88  const std::string& res_file = "");
91  void ExtractAbcSynthesisResultForEnhancement(InvariantInCnf& incremental_cnf,
92  bool autodet = true,
93  bool reachable = true);
94 
96  bool virtual RunVerifAuto(const std::string& script_selection,
97  const std::string& pid_fname = "",
98  bool run_test = false,
99  unsigned timeout = 0);
101  bool virtual RunSynAuto(bool run_test = false);
102 
104  void AcceptAllCandidateInvariant();
107  void PruneCandidateInvariant();
109  void SupplyCandidateInvariant(const std::string& vlg);
111  void ClearAllCandidateInvariants();
112 
113  // -------------------- GrainChc ------------------ //
114  void ChangeGrainSyntax(const std::vector<std::string>& syn);
117  bool WordLevelEnhancement(const InvariantInCnf& incremental_cnf,
118  bool run_test = false);
120  const InvariantInCnf& GetCurrentCnfEnhance() const;
122  void MergeCnf(const InvariantInCnf& incremental_cnf);
124  void ExtractInvariantVarForEnhance(
125  size_t inv_idx, InvariantInCnf& incremental_cnf, bool per_clause,
126  const std::set<std::string>& vars_to_remove = {});
127 
128  // -------------------- ACCESSOR ------------------ //
130  bool in_bad_state() const { return bad_state; }
132  bool check_in_bad_state() const;
134  void LoadDesignSmtInfo(const std::string& fn);
137  const std::vector<std::string>& GetRunnableTargetScriptName() const;
139  void LoadPrevStatisticsState(const std::string& fn);
141  DesignStatistics GetDesignStatistics() const;
143  const InvariantObject& GetInvariants() const;
145  void RemoveInvariantsByIdx(size_t idx);
147  const InvariantObject& GetCandidateInvariants() const;
149  void LoadInvariantsFromFile(const std::string& fn);
151  void LoadCandidateInvariantsFromFile(const std::string& fn);
152 
153 protected:
154  // -------------------- MEMBERS ------------------ //
156  InvariantObject inv_obj;
158  InvariantInCnf inv_cnf;
160  InvariantObject inv_candidate;
162  std::unique_ptr<CexExtractor> cex_extract;
164  std::string vlg_mod_inst_name;
166  cegar_status status;
168  std::shared_ptr<smt::YosysSmtParser> design_smt_info;
170  additional_width_info_t additional_width_info;
172  bool bad_state;
174  unsigned round_id;
176  std::vector<std::string> runnable_script_name;
178  bool verification_pass;
180  std::string vcd_file_name;
182  bool cex_reachable;
184  std::string synthesis_result_fn;
186  enum cur_inv_tp { NONE, GRAIN_CHC, CHC, CEGAR_ABC } current_inv_type;
187 
188  // --------------------------------------------------
189  // for book-keeping purpose
190  // --------------------------------------------------
192  std::vector<std::string> implementation_incl_path;
194  std::vector<std::string> implementation_srcs_path;
196  std::string implementation_top_module_name;
198  std::string refinement_variable_mapping_path;
200  std::string refinement_condition_path;
202  std::string _output_path;
204  InstrLvlAbsPtr _host;
206  verify_backend_selector v_backend;
208  synthesis_backend_selector s_backend;
210  vtg_config_t _vtg_config;
212  VerilogGenerator::VlgGenConfig _vlg_config;
213 
214  // --------------------------------------------------
215  // for statistics purpose
216  // --------------------------------------------------
218  double eqcheck_time;
220  double inv_validate_time;
222  double inv_proof_attempt_time;
224  double inv_syn_time;
226  double inv_enhance_time;
228  std::vector<double> inv_syn_time_series;
229 
230 public:
232  long long total_grain_cand;
233 
234 }; // class InvariantSynthesizerCegar
235 
236 }; // namespace ilang
237 
238 #endif // INVSYN_INTERFACE
239 
240 #endif // ILANG_VTARGET_OUT_INV_SYN_CEGAR_H__
struct ilang::VlgVerifTgtGenBase::_adv_parameters advanced_parameters_t
backend_selector
Definition: vtarget_gen.h:31
struct ilang::VlgVerifTgtGenBase::_vtg_config vtg_config_t
Verilog Target Generation Configuration.
VerilogGeneratorBase::VlgGenConfig VlgGenConfig
the structure to configure the verilog generator
Definition: verilog_gen.h:421
InstrLvlAbs::InstrLvlAbsPtr InstrLvlAbsPtr
Pointer type for normal use of InstrLvlAbs.
Definition: instr_lvl_abs.h:326
synthesis_backend_selector
Type of invariant synthesis backend.
Definition: vtarget_gen.h:45