u_rewriter.h

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#ifndef ILANG_ILA_MNGR_U_REWRITER_H__
#define ILANG_ILA_MNGR_U_REWRITER_H__

#include <ilang/ila/instr_lvl_abs.h>

namespace ilang {

class FuncObjRewrExpr {
public:
  FuncObjRewrExpr(const ExprMap& rule) : rule_(rule) {}

  ExprPtr get(const ExprPtr& e) const;

  bool pre(const ExprPtr& e) const;
  void post(const ExprPtr& e);

protected:
  ExprMap rule_;

  virtual ExprPtr Rewrite(const ExprPtr& e) const;
  virtual ExprPtr RewriteOp(const ExprPtr& e) const;

}; // class FuncObjRewrExpr

class FuncObjRewrIla {
private:
  typedef CnstIlaMap IlaMap;

public:
  FuncObjRewrIla(const IlaMap& ila_map, const ExprMap& expr_map)
      : ila_map_(ila_map), expr_map_(expr_map) {}

  InstrLvlAbsPtr get(const InstrLvlAbsCnstPtr& m) const;

  bool pre(const InstrLvlAbsCnstPtr& src);
  void post(const InstrLvlAbsCnstPtr& src) const;

private:
  IlaMap ila_map_;
  ExprMap expr_map_;

}; // FuncObjRewrIla

class FuncObjFlatIla {

  /* There is currently a problem:
  This func obj calls duplInst which in turn uses rewriteExpr and rewriteExpr
  does not change the host of of state variables, so the flatten expression
  still has the host pointed to their original ILA. This is fine for Verilog
  Gen, which only depends on variable names to generate variables but may not be
  good enough for other purpose.
    - Hongce
  */

private:
  typedef CnstIlaMap IlaMap;

public:
  FuncObjFlatIla(const InstrLvlAbsCnstPtr& top_, const IlaMap& ila_map,
                 const ExprMap& expr_map);

  bool pre(const InstrLvlAbsCnstPtr& src);
  void post(const InstrLvlAbsCnstPtr& src);

private:
  typedef std::stack<ExprPtr> ValidCondStack;

  IlaMap ila_map_;
  ExprMap expr_map_;
  ValidCondStack valid_cond_stack_;
  InstrLvlAbsCnstPtr top_ila_;
}; // FuncObjRewrIla

} // namespace ilang

#endif // ILANG_ILA_MNGR_U_REWRITER_H__