| _reset_vlg | ilang::IntefaceDirectiveRecorder | protected |
| abs_mems | ilang::IntefaceDirectiveRecorder | protected |
| assmpt_inserter_t typedef | ilang::IntefaceDirectiveRecorder | |
| beginsWith(const std::string &c, const std::string &s) | ilang::IntefaceDirectiveRecorder | static |
| Clear(bool reset_vlg) | ilang::IntefaceDirectiveRecorder | |
| CLOCK enum value (defined in ilang::IntefaceDirectiveRecorder) | ilang::IntefaceDirectiveRecorder | |
| ConnectMemory(const std::string &directive, const std::string &ila_state_name, const std::map< unsigned, rport_t > &rports, const std::map< unsigned, wport_t > &wports, int ila_addr_width, int ila_data_width, bool abs_read) | ilang::IntefaceDirectiveRecorder | |
| ConnectModuleInputAddWire(const std::string &short_name, unsigned width) | ilang::IntefaceDirectiveRecorder | protected |
| ConnectModuleOutputAddWire(const std::string &short_name, unsigned width) | ilang::IntefaceDirectiveRecorder | protected |
| GetAbsMemInstString(VerilogGeneratorBase &gen, const std::string &endCond) | ilang::IntefaceDirectiveRecorder | |
| GetVlgModInstString(VerilogGeneratorBase &gen) const | ilang::IntefaceDirectiveRecorder | |
| ila_input_checker_t typedef | ilang::IntefaceDirectiveRecorder | |
| ila_mem_checker_t typedef | ilang::IntefaceDirectiveRecorder | |
| inf_connector_t typedef | ilang::IntefaceDirectiveRecorder | |
| inf_dir_t enum name | ilang::IntefaceDirectiveRecorder | |
| INPUT enum value (defined in ilang::IntefaceDirectiveRecorder) | ilang::IntefaceDirectiveRecorder | |
| input_wires | ilang::IntefaceDirectiveRecorder | protected |
| InsertAbsMemAssmpt(assmpt_inserter_t inserter) | ilang::IntefaceDirectiveRecorder | |
| IntefaceDirectiveRecorder(bool reset_vlg) | ilang::IntefaceDirectiveRecorder | inline |
| internal_wires | ilang::IntefaceDirectiveRecorder | protected |
| isSpecialInputDir(const std::string &c) | ilang::IntefaceDirectiveRecorder | static |
| isSpecialInputDirCompatibleWith(const std::string &c, const SignalInfoBase &vlg_sig) | ilang::IntefaceDirectiveRecorder | static |
| KEEP enum value (defined in ilang::IntefaceDirectiveRecorder) | ilang::IntefaceDirectiveRecorder | |
| KeepMemoryPorts(const std::string &mem_name, const std::string &port_name, bool caller_build_wire) | ilang::IntefaceDirectiveRecorder | |
| MEM_R_A enum value (defined in ilang::IntefaceDirectiveRecorder) | ilang::IntefaceDirectiveRecorder | |
| MEM_R_D enum value (defined in ilang::IntefaceDirectiveRecorder) | ilang::IntefaceDirectiveRecorder | |
| MEM_R_EN enum value (defined in ilang::IntefaceDirectiveRecorder) | ilang::IntefaceDirectiveRecorder | |
| MEM_W_A enum value (defined in ilang::IntefaceDirectiveRecorder) | ilang::IntefaceDirectiveRecorder | |
| MEM_W_D enum value (defined in ilang::IntefaceDirectiveRecorder) | ilang::IntefaceDirectiveRecorder | |
| MEM_W_EN enum value (defined in ilang::IntefaceDirectiveRecorder) | ilang::IntefaceDirectiveRecorder | |
| mod_inst_rec | ilang::IntefaceDirectiveRecorder | protected |
| mod_inst_rec_t typedef | ilang::IntefaceDirectiveRecorder | |
| ModuleInstSanityCheck(VerilogGeneratorBase &gen) const | ilang::IntefaceDirectiveRecorder | protected |
| NC enum value (defined in ilang::IntefaceDirectiveRecorder) | ilang::IntefaceDirectiveRecorder | |
| output_wires | ilang::IntefaceDirectiveRecorder | protected |
| RegisterExtraWire(const std::string &io_name, const std::string &outside_name) | ilang::IntefaceDirectiveRecorder | |
| RegisterInterface(const SignalInfoBase &vlg_sig, const std::string &refstr, ila_input_checker_t chk, ila_mem_checker_t mget) | ilang::IntefaceDirectiveRecorder | |
| RESET enum value (defined in ilang::IntefaceDirectiveRecorder) | ilang::IntefaceDirectiveRecorder | |
| rport_t typedef | ilang::IntefaceDirectiveRecorder | |
| SetMemName(const std::string &directive, const std::string &ila_state_name, bool abs_read) | ilang::IntefaceDirectiveRecorder | |
| SetMemNameAndWidth(const std::string &directive, const std::string &ila_state_name, bool abs_read, int, int) | ilang::IntefaceDirectiveRecorder | |
| SO enum value (defined in ilang::IntefaceDirectiveRecorder) | ilang::IntefaceDirectiveRecorder | |
| START enum value (defined in ilang::IntefaceDirectiveRecorder) | ilang::IntefaceDirectiveRecorder | |
| vlg_sig_t typedef | ilang::IntefaceDirectiveRecorder | |
| vlg_sig_vec_t typedef | ilang::IntefaceDirectiveRecorder | |
| VlgAddTopInteface(VerilogGeneratorBase &gen) const | ilang::IntefaceDirectiveRecorder | |
| wport_t typedef | ilang::IntefaceDirectiveRecorder | |
1.8.5
