ilang::IntefaceDirectiveRecorder Class Reference

Used in Verilog Verification Target Generation for dealing with interface directives. More...

#include <directive.h>

Public Types
enum	inf_dir_t {   KEEP = 0, NC, SO, INPUT,   RESET, CLOCK, MEM_R_A, MEM_R_D,   MEM_R_EN, MEM_W_A, MEM_W_D, MEM_W_EN,   START }
	Type interface directives.
typedef std::pair< inf_dir_t, std::string >	inf_connector_t
	Type of interface connector.
typedef std::map< std::string, inf_connector_t >	mod_inst_rec_t
	Type of interface connector storage.
using	vlg_sig_t = VerilogGeneratorBase::vlg_sig_t
	Using vlg-out's signal type.
using	vlg_sig_vec_t = VerilogGeneratorBase::vlg_sigs_t
	Using vlg-out's signal vector type.
typedef std::function< bool(const std::string &, const SignalInfoBase &)>	ila_input_checker_t
	ILA input compatible checker type.
typedef std::function < std::pair< unsigned, unsigned >const std::string &)>	ila_mem_checker_t
	Type of call back function to find information about a memory.
typedef std::function< void(const std::string &)>	assmpt_inserter_t
	Type of call back function to insert assumptions.
using	rport_t = VerilogGeneratorBase::rport_t
	type of read port
using	wport_t = VerilogGeneratorBase::wport_t
	type of write port

Public Member Functions
	IntefaceDirectiveRecorder (bool reset_vlg)
	Check if an interface needs to be declare as top module I/O. More...
void	Clear (bool reset_vlg)
	clear all internal storage
std::string	GetVlgModInstString (VerilogGeneratorBase &gen) const
	Return a string used for instantiating.
void	VlgAddTopInteface (VerilogGeneratorBase &gen) const
	Add signals to the wrapper_generator.
void	RegisterInterface (const SignalInfoBase &vlg_sig, const std::string &refstr, ila_input_checker_t chk, ila_mem_checker_t mget)
	Used to tell this module about the refinement relations.
void	RegisterExtraWire (const std::string &io_name, const std::string &outside_name)
	Register the extra wire to connect (for extra wire)
std::string	ConnectMemory (const std::string &directive, const std::string &ila_state_name, const std::map< unsigned, rport_t > &rports, const std::map< unsigned, wport_t > &wports, int ila_addr_width, int ila_data_width, bool abs_read)
	Register the connection of signals related to a memory.
void	InsertAbsMemAssmpt (assmpt_inserter_t inserter)
	Insert memory abstractions' assumptions.
void	SetMemName (const std::string &directive, const std::string &ila_state_name, bool abs_read)
void	SetMemNameAndWidth (const std::string &directive, const std::string &ila_state_name, bool abs_read, int, int)
std::string	GetAbsMemInstString (VerilogGeneratorBase &gen, const std::string &endCond)
	Return the memory instantiation string.
std::pair< std::string, unsigned int >	KeepMemoryPorts (const std::string &mem_name, const std::string &port_name, bool caller_build_wire)

Static Public Member Functions
static bool	beginsWith (const std::string &c, const std::string &s)
	Return if a string 'c' begins with string 's'.
static bool	isSpecialInputDir (const std::string &c)
	Return true if 'c' is special input directive.
static bool	isSpecialInputDirCompatibleWith (const std::string &c, const SignalInfoBase &vlg_sig)
	Check for compatibility.

Protected Member Functions
void	ModuleInstSanityCheck (VerilogGeneratorBase &gen) const
void	ConnectModuleInputAddWire (const std::string &short_name, unsigned width)
	a shortcut to connect module and add wire
void	ConnectModuleOutputAddWire (const std::string &short_name, unsigned width)
	a shortcut to connect module and add wire

Protected Attributes
mod_inst_rec_t	mod_inst_rec
	a map of port-name -> (tp, signal name)
vlg_sig_vec_t	input_wires
	wires to be declared as input and wire
vlg_sig_vec_t	output_wires
	wires to be declared as output and wire
vlg_sig_vec_t	internal_wires
	wires to be declared as just wire
std::map< std::string, VlgAbsMem >	abs_mems
	ila-mem-name -> abs
bool	_reset_vlg
	whether to reset this vlg (reset to rst or dummy_reset)

Detailed Description

Used in Verilog Verification Target Generation for dealing with interface directives.

Constructor & Destructor Documentation

ilang::IntefaceDirectiveRecorder::IntefaceDirectiveRecorder ( bool  reset_vlg )

inline

Check if an interface needs to be declare as top module I/O.

Parameters

[in]

:

whether to connect reset signal to rst/dummy_reset The former is for invariants, the latter for instructions

Member Function Documentation

std::pair<std::string, unsigned int> ilang::IntefaceDirectiveRecorder::KeepMemoryPorts	(	const std::string &	mem_name,
		const std::string &	port_name,
		bool	caller_build_wire
	)

Check if some port has been connected, if not, connect it to the wire_name (will not create wire!) if connected, will warn and refuse to connect should be called before GetAbsMemInstString return the wire name to create (but no need to create if it is empty)

void ilang::IntefaceDirectiveRecorder::ModuleInstSanityCheck ( VerilogGeneratorBase &  gen ) const

protected

a sanity check for module instantiation string gen, check if all the vlg module i/o has been declared correctly.

void ilang::IntefaceDirectiveRecorder::SetMemName	(	const std::string &	directive,
		const std::string &	ila_state_name,
		bool	abs_read
	)

Setting the memory abstraction name, but does not enforce any equality there

void ilang::IntefaceDirectiveRecorder::SetMemNameAndWidth	(	const std::string &	directive,
		const std::string &	ila_state_name,
		bool	abs_read,
		int	,
		int
	)

Setting the memory abstraction name, and width... but does not enforce any equality there

---

The documentation for this class was generated from the following file:

• directive.h