ilang
1.1.4
ILAng: A Modeling and Verification Platform for SoCs
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This is the complete list of members for ilang::SignalInfoWire, including all inherited members.
_def | ilang::SignalInfoWire | protected |
_hierarchical_name | ilang::SignalInfoBase | protected |
_loc | ilang::SignalInfoBase | protected |
_name | ilang::SignalInfoBase | protected |
_type | ilang::SignalInfoBase | protected |
_width | ilang::SignalInfoBase | protected |
get_decl_loc() const | ilang::SignalInfoBase | inlinevirtual |
get_def() | ilang::SignalInfoWire | inline |
get_hierarchical_name() const | ilang::SignalInfoBase | inlinevirtual |
get_signal_name() const | ilang::SignalInfoBase | inlinevirtual |
get_type() const | ilang::SignalInfoBase | inlinevirtual |
get_width() const | ilang::SignalInfoBase | inlinevirtual |
is_bad_signal() const | ilang::SignalInfoBase | inlinevirtual |
is_input() const | ilang::SignalInfoBase | inlinevirtual |
is_io_sig() const | ilang::SignalInfoBase | inlinevirtual |
is_output() const | ilang::SignalInfoBase | inlinevirtual |
is_reg() const | ilang::SignalInfoBase | inlinevirtual |
no_internal_def() const | ilang::SignalInfoBase | inlinevirtual |
SignalInfoBase(const std::string &n, const std::string &h, unsigned w, const VerilogAnalyzerBase::hierarchical_name_type &typ, const VerilogAnalyzerBase::vlg_loc_t &loc) | ilang::SignalInfoBase | inline |
SignalInfoWire(ast_net_declaration *def, const std::string &full_name, VerilogAnalyzerBase::hierarchical_name_type tp, const std::map< std::string, int > *const width_info, const VerilogAnalyzer *_ana) | ilang::SignalInfoWire |