Class to hold signal info. More...

Inheritance diagram for ilang::SignalInfoBase:

Public Member Functions
virtual unsigned	get_width () const

virtual bool	is_io_sig () const
	Whether is a IO signal.

virtual bool	no_internal_def () const
	Whether it is defined only at the port.

virtual bool	is_reg () const
	Whether it is a register.

virtual bool	is_input () const
	Whether it is an input signal.

virtual bool	is_output () const
	Whether it is an output signal.

virtual bool	is_bad_signal () const
	Whether this info is usable.

virtual VerilogAnalyzerBase::hierarchical_name_type	get_type () const
	return its type

virtual VerilogAnalyzerBase::vlg_loc_t	get_decl_loc () const
	Return its location.

virtual std::string	get_signal_name () const
	Return is own name.

virtual std::string	get_hierarchical_name () const
	Return its hierarchical name.

	SignalInfoBase (const std::string &n, const std::string &h, unsigned w, const VerilogAnalyzerBase::hierarchical_name_type &typ, const VerilogAnalyzerBase::vlg_loc_t &loc)
	------------------— ACCESSORS ----------------— ///

Protected Attributes
const std::string	_name

const std::string	_hierarchical_name
	full name

const unsigned	_width
	width of the signal

const VerilogAnalyzerBase::hierarchical_name_type	_type
	its type

const VerilogAnalyzerBase::vlg_loc_t	_loc
	its location of definition

Detailed Description

Class to hold signal info.

Member Function Documentation

virtual unsigned ilang::SignalInfoBase::get_width ( ) const

inlinevirtual

------------------— ACCESSORS ----------------— /// Return the width of the signal

const std::string ilang::SignalInfoBase::_name

protected

------------------— MEMBERS ----------------— /// its own name

The documentation for this class was generated from the following file: