| add_always_stmt(const vlg_stmt_t &s) | ilang::VerilogGeneratorBase | |
| add_assign_stmt(const vlg_name_t &l, const vlg_name_t &r) | ilang::VerilogGeneratorBase | |
| add_external_mem(const vlg_name_t &mem_name, int addr_width, int data_width, int entry_num) | ilang::VerilogGeneratorBase | |
| add_init_stmt(const vlg_stmt_t &s) | ilang::VerilogGeneratorBase | |
| add_input(const vlg_name_t &n, int w) | ilang::VerilogGeneratorBase | |
| add_internal_mem(const vlg_name_t &mem_name, int addr_width, int data_width, int entry_num) | ilang::VerilogGeneratorBase | |
| add_ite_stmt(const vlg_stmt_t &cond, const vlg_stmt_t &tstmt, const vlg_stmt_t &fstmt) | ilang::VerilogGeneratorBase | |
| add_output(const vlg_name_t &n, int w) | ilang::VerilogGeneratorBase | |
| add_preheader(const vlg_stmt_t &stmt) | ilang::VerilogGeneratorBase | |
| add_reg(const vlg_name_t &n, int w) | ilang::VerilogGeneratorBase | |
| add_stmt(const vlg_stmt_t &s) | ilang::VerilogGeneratorBase | |
| add_wire(const vlg_name_t &n, int w, bool keep=false) | ilang::VerilogGeneratorBase | |
| all_valid_names | ilang::VerilogGeneratorBase | protected |
| always_stmts | ilang::VerilogGeneratorBase | protected |
| AnnotateMemory(const memory_export_annotation_t &annotation) | ilang::VerilogGeneratorBase | |
| cfg_ | ilang::VerilogGeneratorBase | protected |
| check_reserved_name(const vlg_name_t &n) const | ilang::VerilogGeneratorBase | protected |
| clkName | ilang::VerilogGeneratorBase | protected |
| cmap | ilang::VerilogGeneratorBase | protected |
| CnstMap typedef | ilang::VerilogGeneratorBase | |
| counterName | ilang::VerilogGeneratorBase | protected |
| current_writes | ilang::VerilogGeneratorBase | protected |
| decodeAccName | ilang::VerilogGeneratorBase | protected |
| decodeNames | ilang::VerilogGeneratorBase | protected |
| DumpToFile(std::ostream &fout) const | ilang::VerilogGeneratorBase | virtual |
| ExportIla(const InstrLvlAbsPtr &ila_ptr_) | ilang::VerilogGenerator | |
| ExportTopLevelInstr(const InstrPtr &instr_ptr_) | ilang::VerilogGenerator | |
| ExprMap typedef | ilang::VerilogGenerator | |
| func_ptr_set | ilang::VerilogGeneratorBase | protected |
| function_app_t typedef | ilang::VerilogGenerator | |
| function_app_vec_t typedef | ilang::VerilogGenerator | |
| get_width(const ExprPtr &n) | ilang::VerilogGeneratorBase | protectedstatic |
| grantAccName | ilang::VerilogGeneratorBase | protected |
| idCounter | ilang::VerilogGeneratorBase | protected |
| ila_func_app | ilang::VerilogGeneratorBase | protected |
| ila_rports | ilang::VerilogGeneratorBase | protected |
| ila_wports | ilang::VerilogGeneratorBase | protected |
| IlaBoolValType typedef | ilang::VerilogGeneratorBase | |
| IlaBvValType typedef | ilang::VerilogGeneratorBase | |
| IlaBvValUnsignedType typedef | ilang::VerilogGeneratorBase | |
| init_assumpts | ilang::VerilogGeneratorBase | protected |
| init_stmts | ilang::VerilogGeneratorBase | protected |
| inputs | ilang::VerilogGeneratorBase | protected |
| ite_stmts | ilang::VerilogGeneratorBase | protected |
| mem_i | ilang::VerilogGeneratorBase | protected |
| mem_o | ilang::VerilogGeneratorBase | protected |
| mem_probe_o | ilang::VerilogGeneratorBase | protected |
| mem_write_entry_list_stack_t typedef | ilang::VerilogGenerator | |
| mem_write_entry_list_t typedef | ilang::VerilogGenerator | |
| mem_write_entry_t typedef | ilang::VerilogGenerator | |
| mem_write_list_t typedef | ilang::VerilogGenerator | |
| mem_write_t typedef | ilang::VerilogGenerator | |
| memory_export_annotation (defined in ilang::VerilogGeneratorBase) | ilang::VerilogGeneratorBase | protected |
| memory_export_annotation_t typedef | ilang::VerilogGeneratorBase | |
| mems_external | ilang::VerilogGeneratorBase | protected |
| mems_internal | ilang::VerilogGeneratorBase | protected |
| moduleName | ilang::VerilogGeneratorBase | protected |
| new_id() | ilang::VerilogGeneratorBase | protected |
| new_id(const ExprPtr &e) | ilang::VerilogGeneratorBase | protected |
| nmap | ilang::VerilogGeneratorBase | protected |
| outputs | ilang::VerilogGeneratorBase | protected |
| past_writes | ilang::VerilogGeneratorBase | protected |
| preheader | ilang::VerilogGeneratorBase | protected |
| reference_name_set | ilang::VerilogGeneratorBase | protected |
| regs | ilang::VerilogGeneratorBase | protected |
| rstName | ilang::VerilogGeneratorBase | protected |
| sanitizeName(const vlg_name_t &n) | ilang::VerilogGeneratorBase | static |
| sanitizeName(const ExprPtr &n) | ilang::VerilogGeneratorBase | static |
| startName | ilang::VerilogGeneratorBase | protected |
| state_update_ite_unknown | ilang::VerilogGeneratorBase | protected |
| state_update_ite_unknown_map_t typedef (defined in ilang::VerilogGeneratorBase) | ilang::VerilogGeneratorBase | |
| statements | ilang::VerilogGeneratorBase | protected |
| TestVerilogExport class | ilang::VerilogGenerator | friend |
| ToVlgNum(IlaBvValType value, unsigned width) | ilang::VerilogGeneratorBase | static |
| validName | ilang::VerilogGeneratorBase | protected |
| VerilogGenerator(const VlgGenConfig &config=VlgGenConfig(), const std::string &modName="", const std::string &clk="clk", const std::string &rst="rst") | ilang::VerilogGenerator | |
| VerilogGeneratorBase(const VlgGenConfig &config=VlgGenConfig(), const std::string &modName="", const std::string &clk="clk", const std::string &rst="rst") | ilang::VerilogGeneratorBase | |
| vlg_addr_t typedef | ilang::VerilogGenerator | |
| vlg_const_t typedef | ilang::VerilogGeneratorBase | |
| vlg_data_t typedef | ilang::VerilogGenerator | |
| vlg_ite_stmt_t typedef | ilang::VerilogGenerator | |
| vlg_ite_stmts_t typedef | ilang::VerilogGenerator | |
| vlg_mem_t typedef | ilang::VerilogGenerator | |
| vlg_mems_rec_t typedef | ilang::VerilogGenerator | |
| vlg_name_t typedef | ilang::VerilogGenerator | |
| vlg_names_t typedef | ilang::VerilogGenerator | |
| vlg_sig_keep_t typedef | ilang::VerilogGenerator | |
| vlg_sig_t typedef | ilang::VerilogGenerator | |
| vlg_sigs_map_t typedef | ilang::VerilogGeneratorBase | |
| vlg_sigs_set_t typedef | ilang::VerilogGenerator | |
| vlg_sigs_t typedef | ilang::VerilogGenerator | |
| vlg_stmt_t typedef | ilang::VerilogGenerator | |
| vlg_stmts_t typedef | ilang::VerilogGenerator | |
| VlgGenConfig typedef | ilang::VerilogGenerator | |
| WidthToRange(int w) | ilang::VerilogGeneratorBase | protectedstatic |
| wires | ilang::VerilogGeneratorBase | protected |
| wires_keep | ilang::VerilogGeneratorBase | protected |