ilang::VerilogGeneratorBase Class Reference

Base class of VerilogGenerator. More...

#include <verilog_gen.h>

Inheritance diagram for ilang::VerilogGeneratorBase:

Classes
struct	function_app_t
	Type of app func. More...
struct	mem_write_entry_t
	This is type of an individual write. More...
struct	mem_write_t
	This is the write and its associated condition. More...
struct	rport_t
	type of read port More...
struct	state_update_unknown
	Type of ite update unknown. More...
struct	VlgGenConfig
	the structure to configure the verilog generator More...
struct	wport_t
	type of write port More...

Public Types
using	IlaBoolValType = bool
	The type of bool value in ila.
using	IlaBvValType = BvVal::BvValType
	The type of bitvector value in ila.
using	IlaBvValUnsignedType = BvVal::BvValType
	The unsigned type of bitvector value in ila.
typedef std::string	vlg_name_t
	Type of Verilog id names.
typedef std::string	vlg_stmt_t
	Type of Verilog statement.
typedef std::string	vlg_const_t
	Type of Verilog constants.
typedef std::string	vlg_addr_t
	Type of Verilog address.
typedef std::string	vlg_data_t
	Type of Verilog data.
typedef std::vector< vlg_name_t >	vlg_stmts_t
	Type of Verilog statements (a vector)
typedef std::vector< vlg_name_t >	vlg_names_t
	Type of Verilog names (a vector)
typedef std::pair< vlg_name_t, int >	vlg_sig_t
	Type of Verilog signal, name & bw.
typedef std::vector< vlg_sig_t >	vlg_sigs_t
	Type of Verilog signals (a vector)
typedef std::map< vlg_name_t, int >	vlg_sigs_map_t
	Type of Verilog signals (a vector)
typedef std::map< vlg_name_t, bool >	vlg_sig_keep_t
	Type of a map: name -> need to add keep?
typedef std::set< vlg_sig_t >	vlg_sigs_set_t
	Type of set of Verilog signals.
typedef std::tuple< vlg_stmt_t, vlg_stmt_t, vlg_stmt_t >	vlg_ite_stmt_t
	Type of Verilog ITEs (IN sequential block)
typedef std::vector < vlg_ite_stmt_t >	vlg_ite_stmts_t
	Type of Verilog ITEs statements.
typedef std::tuple< vlg_name_t, int, int, int >	vlg_mem_t
	Type of the memorys that are going to be created.
typedef std::map< vlg_name_t, vlg_mem_t >	vlg_mems_rec_t
	Type of collection of memorys.
typedef std::list < mem_write_entry_t >	mem_write_entry_list_t
	This is type of a list of writes.
typedef std::list < mem_write_entry_list_t >	mem_write_entry_list_stack_t
	Type of a stack of writes use in visitMemNodes.
typedef std::list< mem_write_t >	mem_write_list_t
	List of writes w. associated conditions.
typedef std::vector < function_app_t >	function_app_vec_t
typedef std::map< std::string, state_update_unknown >	state_update_ite_unknown_map_t
typedef std::unordered_map < const ExprPtr, vlg_name_t, VerilogGenHash >	ExprMap
	Type for caching the generated expressions.
typedef std::map< std::pair < IlaBvValType, unsigned > , vlg_name_t >	CnstMap
	Type for cacheing the constant.
typedef std::map< std::string, bool >	memory_export_annotation_t
	Type for memory annotation.

Public Member Functions
void	add_input (const vlg_name_t &n, int w)
	record an input signal
void	add_output (const vlg_name_t &n, int w)
	record an output signal
void	add_wire (const vlg_name_t &n, int w, bool keep=false)
	record a wire
void	add_reg (const vlg_name_t &n, int w)
	record a register
void	add_stmt (const vlg_stmt_t &s)
	record a stmt (outside the always block)
void	add_assign_stmt (const vlg_name_t &l, const vlg_name_t &r)
	record an assignment stmt (outside the always block), will call add_stmt
void	add_always_stmt (const vlg_stmt_t &s)
void	add_init_stmt (const vlg_stmt_t &s)
	record an assignemnt in the always block (in if(rst) branch )
void	add_ite_stmt (const vlg_stmt_t &cond, const vlg_stmt_t &tstmt, const vlg_stmt_t &fstmt)
void	add_internal_mem (const vlg_name_t &mem_name, int addr_width, int data_width, int entry_num)
	record an internal memory
void	add_external_mem (const vlg_name_t &mem_name, int addr_width, int data_width, int entry_num)
	record an external memory
void	add_preheader (const vlg_stmt_t &stmt)
	add an item to the preheader
	VerilogGeneratorBase (const VlgGenConfig &config=VlgGenConfig(), const std::string &modName="", const std::string &clk="clk", const std::string &rst="rst")
virtual void	DumpToFile (std::ostream &fout) const
void	AnnotateMemory (const memory_export_annotation_t &annotation)
	add memory annotation, please invoke right after constructor

Static Public Member Functions
static vlg_name_t	sanitizeName (const vlg_name_t &n)
	sanitize a name string, so it will generate illegal verilog identifier
static vlg_name_t	sanitizeName (const ExprPtr &n)
static vlg_const_t	ToVlgNum (IlaBvValType value, unsigned width)
	will force to be hex

Protected Member Functions
bool	check_reserved_name (const vlg_name_t &n) const
	Check if a name is reserved (clk/rst/modulename/decodeName/ctrName)
vlg_name_t	new_id ()
	get a new id
vlg_name_t	new_id (const ExprPtr &e)

Static Protected Member Functions
static int	get_width (const ExprPtr &n)
	Get the width of an ExprPtr, must be supported sort.
static std::string	WidthToRange (int w)
	convert a widith to a verilog string

Protected Attributes
vlg_name_t	moduleName
	Verilog Module Name.
vlg_name_t	clkName
	Clock signal name.
vlg_name_t	rstName
	Reset signal name.
vlg_names_t	decodeNames
vlg_name_t	validName
vlg_name_t	startName
	start signal name, may not be used
vlg_sig_t	grantAccName
vlg_sig_t	decodeAccName
	accumulated decode signals
vlg_name_t	counterName
	The name of internal counter.
vlg_sigs_map_t	inputs
	vector of input signals
vlg_sigs_map_t	outputs
	vector of output signals
vlg_sigs_t	mem_i
	vector of memory input signals
vlg_sigs_t	mem_o
	vector of memory output signals
vlg_sigs_t	mem_probe_o
	vector of signals that probe each element of a memory
vlg_sigs_map_t	wires
	vector of wires to be defined
vlg_sig_keep_t	wires_keep
	a map to store if a wire needs to keep
vlg_sigs_t	regs
	vector of regs to be defined
vlg_mems_rec_t	mems_internal
	vector of mems to be defined
vlg_mems_rec_t	mems_external
	vector of mems from outside (will not be defined)
vlg_stmts_t	init_stmts
vlg_stmts_t	init_assumpts
vlg_stmts_t	statements
	statements to be outside the always block
vlg_stmts_t	always_stmts
	statements to be used in the always block but out of the reset
vlg_ite_stmts_t	ite_stmts
vlg_stmt_t	preheader
	For auxiliary definitions.
ExprMap	nmap
	The map to cache the expression (we only need to store the name)
CnstMap	cmap
mem_write_list_t	current_writes
	For traverse a mem expression.
mem_write_list_t	past_writes
vlg_sigs_set_t	all_valid_names
	to hold all valid names, a sanity check
std::map< std::string, std::map< unsigned, rport_t > >	ila_rports
std::map< std::string, std::map< unsigned, wport_t > >	ila_wports
	ila write ports
function_app_vec_t	ila_func_app
	a collection of all function application
state_update_ite_unknown_map_t	state_update_ite_unknown
	a collection of all state update ite unknown
memory_export_annotation_t	memory_export_annotation
unsigned	idCounter
	The id counter.
const VlgGenConfig	cfg_
	The configuration.
std::map< std::string, std::string >	reference_name_set
	reference name list
std::set< FuncPtr >	func_ptr_set

Friends
class	TestVerilogExport
	let the test class use this module
class	VlgSglTgtGen
	let VlgVerifTgtGen use this module to generate the wrapper module
class	IntefaceDirectiveRecorder
std::ostream &	operator<< (std::ostream &out, const mem_write_entry_t &mwe)
std::ostream &	operator<< (std::ostream &out, const mem_write_entry_list_t &mwel)
std::ostream &	operator<< (std::ostream &out, const mem_write_entry_list_stack_t &mwel)
std::ostream &	operator<< (std::ostream &out, const mem_write_t &mw)
std::ostream &	operator<< (std::ostream &out, const mem_write_list_t &mwl)

Detailed Description

Base class of VerilogGenerator.

Constructor & Destructor Documentation

ilang::VerilogGeneratorBase::VerilogGeneratorBase	(	const VlgGenConfig &	config = VlgGenConfig(),
		const std::string &	modName = "",
		const std::string &	clk = "clk",
		const std::string &	rst = "rst"
	)

Parameters

[in]	Configuration
[in]	Top	module name, if empty, get it from instruction name
[in]	clock	signal name
[in]	reset	signal name

Member Function Documentation

void ilang::VerilogGeneratorBase::add_always_stmt

(

const vlg_stmt_t &

s

)

record an assignment in the always block (after the reset, in the else branch, guarded by the valid condition )

void ilang::VerilogGeneratorBase::add_ite_stmt	(	const vlg_stmt_t &	cond,
		const vlg_stmt_t &	tstmt,
		const vlg_stmt_t &	fstmt
	)

record an ite assignment, (after the reset, in the else branch, guarded by the valid condition ), (if fstmt == "", will not generate its else block)

virtual void ilang::VerilogGeneratorBase::DumpToFile ( std::ostream &  fout ) const

virtual

after parsing either the Instruction/ILA, use this function to dump to a file.

vlg_name_t ilang::VerilogGeneratorBase::new_id ( const ExprPtr &  e )

protected

if the exprptr contains some meaning in its name, will try to incorporate that to the name;

static vlg_name_t ilang::VerilogGeneratorBase::sanitizeName ( const ExprPtr &  n )

static

sanitize the name of an expr, so it will generate illegal verilog identifier

Friends And Related Function Documentation

friend class IntefaceDirectiveRecorder

friend

let IntefaceDirectiveRecorder use this module to generate the wrapper module

Member Data Documentation

CnstMap ilang::VerilogGeneratorBase::cmap

protected

The map to cache the constants (o.w. there will be overhead, as each constant may appear multiple times)

vlg_names_t ilang::VerilogGeneratorBase::decodeNames

protected

Output signals that allows to determine if an instruction's decode is true, not need for width

std::set<FuncPtr> ilang::VerilogGeneratorBase::func_ptr_set

protected

Set of functions that need to be translated, we will collect this while translating the exprs

vlg_sig_t ilang::VerilogGeneratorBase::grantAccName

protected

An input, that can be used to control which instruction you would like to execute if more than one is ready you can assume in JasperGold that: $onehot(grant) && ( grant & decodeAccName == grant ) to enforce that: you only grant to one and only one instruction whose decode is true. another approach is to set grant to all 1s.

std::map<std::string, std::map<unsigned, rport_t> > ilang::VerilogGeneratorBase::ila_rports

protected

To record which mem interface signal correspond to what... ila read ports

vlg_stmts_t ilang::VerilogGeneratorBase::init_assumpts

protected

The other part will be put into SVA assumptions, and the module will have a sparate counter to enforce the assumptions

vlg_stmts_t ilang::VerilogGeneratorBase::init_stmts

protected

statements to be used when reset, for initial conditions, it will try to translate, but won't guarantee

vlg_ite_stmts_t ilang::VerilogGeneratorBase::ite_stmts

protected

statements to be used in the always block but out of the reset with ITE conditions

mem_write_list_t ilang::VerilogGeneratorBase::past_writes

protected

For traverse a mem expression, hold a pointer to the writes, so they will not be destroyed before used

vlg_name_t ilang::VerilogGeneratorBase::validName

protected

Output signals that allows to determine if an instruction's valid is true, not need for width

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The documentation for this class was generated from the following file:

• verilog_gen.h