vlg_mod.h

// ---Hongce Zhang (hongcez@princeton.edu)

#ifndef ILANG_VTARGET_OUT_VLG_MOD_H__
#define ILANG_VTARGET_OUT_VLG_MOD_H__

#include <map>
#include <string>
#include <vector>

#include <ilang/verilog-in/verilog_analysis_wrapper.h>

namespace ilang {

class VerilogModifier {
public:
  // ---------------------- TYPE ------------------------- //
  typedef std::tuple<long,        // lineno
                     std::string, // varname (short name)
                     bool>
      info_t;
  typedef std::map<std::string, // file name
                   std::vector<info_t>>
      fn_l_map_t;
  typedef std::tuple<long,        // lineno
                                  // std::string, // module name
                     std::string, // varname to add a__DOT__b__DOT__ ...
                     unsigned>    // width
      mod_decl_item_t;

  typedef std::tuple<long,        // lineno
                                  // std::string, // instance name
                     std::string, // varname to add a__DOT__b__DOT__ ...
                     unsigned>    // width
      mod_inst_item_t;

  typedef std::tuple<long,        // lineno
                     std::string, // varname
                     unsigned,    // width
                     std::string> // short_sig_name;
      assign_item_t;

  typedef std::tuple<long,        // lineno
                     std::string> // stmt
      add_stmt_t;

  typedef std::map<std::string, // file name
                   std::vector<mod_decl_item_t>>
      mod_decl_map_t;

  typedef std::map<std::string, // file name
                   std::vector<mod_inst_item_t>>
      mod_inst_map_t;

  typedef std::map<std::string, // file name
                   std::vector<assign_item_t>>
      assign_map_t;

  typedef std::map<std::string, // filename
                   std::vector<add_stmt_t>>
      add_stmt_map_t;

  typedef std::pair<std::string, unsigned> vlg_sig_t;

  typedef enum { AUTO = 0, NEW = 1, OLD = 2 } port_decl_style_t;

public:
  VerilogModifier(VerilogInfo* _vlg_info_ptr, port_decl_style_t port_decl_style,
                  bool add_keep_or_not,
                  const std::map<std::string, int>& _sup_width_info); //
  ~VerilogModifier();
  void ReadModifyWrite(const std::string& filename, std::istream& fin,
                       std::ostream& fout);
  void FinishRecording();
  void RecordKeepSignalName(const std::string& vname);
  vlg_sig_t RecordConnectSigName(const std::string& vlg_sig_name,
                                 const std::string& suffix = "");
  void RecordAdditionalVlgModuleStmt(const std::string& stmt,
                                     const std::string& mod_instance_name);

protected:
  // --------------- MEMBERS ---------------------------- //
  fn_l_map_t fn_l_map;
  mod_decl_map_t mod_decl_map;
  mod_inst_map_t mod_inst_map;
  assign_map_t assign_map;
  add_stmt_map_t add_stmt_map;
  VerilogInfo* vlg_info_ptr;
  port_decl_style_t _port_decl_style;
  bool _add_keep_or_not;
  const std::map<std::string, int>& sup_width_info;

protected:
  // --------------- HELPERS --------------------------- //
  static std::string add_keep_to_port(const std::string& line_in,
                                      const std::string& vname);
  static std::string add_keep_to_a_line(const std::string& line_in,
                                        const std::string& vname);
  static std::string
  add_assign_wire_to_this_line(const std::string& line_in,
                               const std::string& vname, unsigned width,
                               const std::string& short_name);
  bool add_mod_decl_wire_to_this_line(const std::string& line_in,
                                      std::string& line_out,
                                      const std::string& vname, unsigned width);
  bool add_mod_inst_wire_to_this_line(const std::string& line_in,
                                      std::string& line_out,
                                      const std::string& vname, unsigned width);

}; // class VerilogModifier

}; // namespace ilang

#endif // ILANG_VTARGET_OUT_VLG_MOD_H__