ilang
1.1.4
ILAng: A Modeling and Verification Platform for SoCs
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the class for modification to verilog More...
#include <vlg_mod.h>
Public Types | |
enum | port_decl_style_t { AUTO = 0, NEW = 1, OLD = 2 } |
The style or port declaration. | |
typedef std::tuple< long, std::string, bool > | info_t |
a tuple to store all related info for modification | |
typedef std::map< std::string, std::vector< info_t > > | fn_l_map_t |
filename -> (lineno, varname, is_port_sig) vec | |
typedef std::tuple< long, std::string, unsigned > | mod_decl_item_t |
type of a module decl modification item | |
typedef std::tuple< long, std::string, unsigned > | mod_inst_item_t |
type of a module inst modification item | |
typedef std::tuple< long, std::string, unsigned, std::string > | assign_item_t |
type of an wire assignment modification item | |
typedef std::tuple< long, std::string > | add_stmt_t |
type of an additional statement of an module | |
typedef std::map< std::string, std::vector< mod_decl_item_t > > | mod_decl_map_t |
type of decl modification record | |
typedef std::map< std::string, std::vector< mod_inst_item_t > > | mod_inst_map_t |
type of a module inst modification record | |
typedef std::map< std::string, std::vector< assign_item_t > > | assign_map_t |
type of an wire assignment modification record | |
typedef std::map< std::string, std::vector< add_stmt_t > > | add_stmt_map_t |
type of additional stmt modification record | |
typedef std::pair< std::string, unsigned > | vlg_sig_t |
type of an wire name w. width | |
Public Member Functions | |
VerilogModifier (VerilogInfo *_vlg_info_ptr, port_decl_style_t port_decl_style, bool add_keep_or_not, const std::map< std::string, int > &_sup_width_info) | |
Constructor: More... | |
~VerilogModifier () | |
Destructor: | |
void | ReadModifyWrite (const std::string &filename, std::istream &fin, std::ostream &fout) |
void | FinishRecording () |
do some work (sorting) | |
void | RecordKeepSignalName (const std::string &vname) |
record the name to add a keep there | |
vlg_sig_t | RecordConnectSigName (const std::string &vlg_sig_name, const std::string &suffix="") |
record the name to add related wires | |
void | RecordAdditionalVlgModuleStmt (const std::string &stmt, const std::string &mod_instance_name) |
record the stmt to be added to a module | |
Protected Attributes | |
fn_l_map_t | fn_l_map |
the record of where to insert keep | |
mod_decl_map_t | mod_decl_map |
decl modification record | |
mod_inst_map_t | mod_inst_map |
a module inst modification record | |
assign_map_t | assign_map |
an wire assignment modification record | |
add_stmt_map_t | add_stmt_map |
a additional stmt modification record | |
VerilogInfo * | vlg_info_ptr |
The pointer object so we can get verilog information of the implementation. | |
port_decl_style_t | _port_decl_style |
cache the style | |
bool | _add_keep_or_not |
whether to add keep | |
const std::map< std::string, int > & | sup_width_info |
the supplementary width info | |
the class for modification to verilog
ilang::VerilogModifier::VerilogModifier | ( | VerilogInfo * | _vlg_info_ptr, |
port_decl_style_t | port_decl_style, | ||
bool | add_keep_or_not, | ||
const std::map< std::string, int > & | _sup_width_info | ||
) |
Constructor:
[in] | pointer | to a verilog info class |
[in] | the | style: 0 auto deteremined, 1 Old, 2 New |
void ilang::VerilogModifier::ReadModifyWrite | ( | const std::string & | filename, |
std::istream & | fin, | ||
std::ostream & | fout | ||
) |
do the work : read from fin and append to fout, fout needs to be open with append option