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vtarget_gen_inv_enhance.h
1 
8 // ---Hongce Zhang
9 
10 #ifndef VTARGET_GEN_INV_ENHANCE_H__
11 #define VTARGET_GEN_INV_ENHANCE_H__
12 
13 #include <ilang/config.h>
14 #ifdef INVSYN_INTERFACE
15 
17 #include <ilang/smt-inout/yosys_smt_parser.h>
18 #include <ilang/vtarget-out/inv-syn/inv_cnf.h>
19 #include <ilang/vtarget-out/vlg_mod.h>
20 #include <ilang/vtarget-out/vtarget_gen_impl.h>
21 #include <iostream>
22 #include <memory>
23 #include <string>
24 #include <vector>
25 
26 namespace ilang {
27 
28 class VlgSglTgtGen_Chc_wCNF;
29 
31 class Chc_enhance_problem {
32  friend class VlgSglTgtGen_Chc_wCNF;
34  typedef std::vector<std::string> prop_t;
37  typedef struct {
38  // the name in [??]
39  // std::string problem_name;
41  prop_t exprs;
42  } problem_t;
44  typedef std::map<std::string, problem_t> problemset_t;
45 
46 protected:
48  problemset_t assumptions;
50  problemset_t assertions;
51 
52 }; // Chc_enhance_problem
53 
55 class VlgSglTgtGen_Chc_wCNF : public VlgSglTgtGen {
56 
57 public:
59  using target_type_t = VlgSglTgtGen::target_type_t;
61  using info_t = VerilogModifier::info_t;
63  using fn_l_map_t = VerilogModifier::fn_l_map_t;
65  using advanced_parameters_t = VlgVerifTgtGenBase::advanced_parameters_t;
67  using _chc_target_t = VlgVerifTgtGenBase::_chc_target_t;
68 
69 public:
70  // --------------------- CONSTRUCTOR ---------------------------- //
84  VlgSglTgtGen_Chc_wCNF(
85  const std::string& output_path, // will be a sub directory of the
86  // output_path of its parent
87  const InstrPtr& instr_ptr, // which could be an empty pointer, and it will
88  // be used to verify invariants
89  const InstrLvlAbsPtr& ila_ptr,
90  const VerilogGenerator::VlgGenConfig& config, nlohmann::json& _rf_vmap,
91  nlohmann::json& _rf_cond, VlgTgtSupplementaryInfo& _sup_info,
92  VerilogInfo* _vlg_info_ptr, const std::string& vlg_mod_inst_name,
93  const std::string& ila_mod_inst_name, const std::string& wrapper_name,
94  const std::vector<std::string>& implementation_srcs,
95  const std::vector<std::string>& include_dirs,
96  const vtg_config_t& vtg_config, backend_selector vbackend,
97  synthesis_backend_selector sbackend, const target_type_t& target_tp,
98  advanced_parameters_t* adv_ptr, bool generate_proof,
99  _chc_target_t chc_target);
100 
101  // --------------------- Destructor ---------------------------- //
103  virtual ~VlgSglTgtGen_Chc_wCNF();
104 
105 protected:
107  Chc_enhance_problem _problems;
109  std::string chc_prob_fname;
111  std::string chc_run_script_name;
113  std::vector<std::string> vlg_mod_inv_vec;
115  synthesis_backend_selector s_backend;
117  std::shared_ptr<smt::YosysSmtParser> design_smt_info;
119  bool generate_proof;
121  bool has_cex;
123  _chc_target_t chc_target;
124 
125 protected:
127  virtual void add_a_direct_assumption(const std::string& aspt,
128  const std::string& dspt) override;
130  virtual void add_a_direct_assertion(const std::string& asst,
131  const std::string& dspt) override;
132 
134  void virtual PreExportProcess() override;
136  virtual void Export_script(const std::string& script_name)
137  override; // do nothing - should not be used
138  virtual void Export_script(const std::string& script_name,
139  const std::string& cnf_fn);
141  virtual void Export_problem(const std::string& extra_name) override;
145  virtual void Export_mem(const std::string& mem_name) override;
147  virtual void Export_modify_verilog() override;
149  void Export_cnf(const InvariantInCnf& cnf, const std::string& cnf_fn) const;
151  void Export_coci(const InvariantInCnf& cnf, const std::string& cnf_fn) const;
152 
153 private:
155  void convert_smt_to_chc_datatype(const std::string& smt_fname,
156  const std::string& chc_fname);
158  void design_only_gen_smt(const std::string& smt_name,
159  const std::string& ys_script_name);
160 
161 public:
163  void virtual ExportAll(const std::string& wrapper_name,
164  const std::string& ila_vlg_name,
165  const std::string& script_name,
166  const std::string& extra_name,
167  const std::string& mem_name) override;
169  void virtual ExportAll(const std::string& wrapper_name,
170  const std::string& ila_vlg_name,
171  const std::string& script_name,
172  const std::string& extra_name,
173  const std::string& mem_name,
174  const std::string& cnf_name,
175  const InvariantInCnf& cnf);
177  std::shared_ptr<smt::YosysSmtParser> GetDesignSmtInfo() const;
179  virtual void do_not_instantiate(void) override{};
180 
181 }; // class VlgVerifTgtGenChc
182 
183 }; // namespace ilang
184 
185 #endif // INVSYN_INTERFACE
186 
187 #endif // VTARGET_GEN_INV_ENHANCE_H__
std::tuple< long, std::string, bool > info_t
a tuple to store all related info for modification
Definition: vlg_mod.h:29
struct ilang::VlgVerifTgtGenBase::_adv_parameters advanced_parameters_t
Instr::InstrPtr InstrPtr
Pointer type for normal use of Instr.
Definition: instr.h:132
target_type_t
Type of the target.
Definition: vtarget_gen_impl.h:40
VerilogGeneratorBase::VlgGenConfig VlgGenConfig
the structure to configure the verilog generator
Definition: verilog_gen.h:421
std::map< std::string, std::vector< info_t > > fn_l_map_t
filename -&gt; (lineno, varname, is_port_sig) vec
Definition: vlg_mod.h:33
InstrLvlAbs::InstrLvlAbsPtr InstrLvlAbsPtr
Pointer type for normal use of InstrLvlAbs.
Definition: instr_lvl_abs.h:326
_chc_target_t
Type of the chc target.
Definition: vtarget_gen.h:53