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vtarget_gen_jasper.h
1 // ---Hongce Zhang
3 
4 #ifndef ILANG_VTARGET_OUT_VTARGET_GEN_JASPER_H__
5 #define ILANG_VTARGET_OUT_VTARGET_GEN_JASPER_H__
6 
7 #include <ilang/vtarget-out/vtarget_gen_impl.h>
8 
9 namespace ilang {
10 
19 
20 public:
21  // --------------------- CONSTRUCTOR ---------------------------- //
36  const std::string& output_path, // will be a sub directory of the
37  // output_path of its parent
38  const InstrPtr& instr_ptr, // which could be an empty pointer, and it will
39  // be used to verify invariants
40  const InstrLvlAbsPtr& ila_ptr,
41  const VerilogGenerator::VlgGenConfig& config, nlohmann::json& _rf_vmap,
42  nlohmann::json& _rf_cond, VlgTgtSupplementaryInfo& _supplementary_info,
43  VerilogInfo* _vlg_info_ptr, const std::string& vlg_mod_inst_name,
44  const std::string& ila_mod_inst_name, const std::string& wrapper_name,
45  const std::vector<std::string>& implementation_srcs,
46  const std::vector<std::string>& include_dirs,
47  const vtg_config_t& vtg_config, backend_selector backend,
48  const target_type_t& target_tp, advanced_parameters_t* adv_ptr);
49 
54  void add_addition_clock_info(const std::string& expr);
55  void add_addition_reset_info(const std::string& expr);
56 
57 protected:
60  std::vector<std::pair<std::string, std::string>> assumptions;
62  std::vector<std::pair<std::string, std::string>> assertions;
64  std::vector<std::string>
65  additional_clock_expr; // we don't put the "clk" here, as by default it
66  // will be there
68  std::vector<std::string> additional_reset_expr;
70  std::string jg_script_name;
72  std::string abs_mem_name;
73 
74 protected:
76  virtual void add_an_assumption(const std::string& aspt,
77  const std::string& dspt) override;
79  virtual void add_an_assertion(const std::string& asst,
80  const std::string& dspt) override;
82  virtual void add_a_direct_assumption(const std::string& aspt,
83  const std::string& dspt) override;
85  virtual void add_a_direct_assertion(const std::string& asst,
86  const std::string& dspt) override;
87 
90  virtual void add_wire_assign_assumption(const std::string& varname,
91  const std::string& expression,
92  const std::string& dspt) override;
95  virtual void add_reg_cassign_assumption(const std::string& varname,
96  const std::string& expression,
97  int width, const std::string& cond,
98  const std::string& dspt) override;
99 
101  void virtual PreExportProcess() override {}
103  virtual void Export_script(const std::string& script_name) override;
105  virtual void
106  Export_problem(const std::string& extra_name) override; // only for cosa
110  virtual void Export_mem(const std::string& mem_name) override;
112  virtual void Export_modify_verilog() override;
113 
114 public:
116  virtual void do_not_instantiate(void) override{};
117 
118 }; // class VlgVerifTgtGenCosaJasper
119 
120 }; // namespace ilang
121 
122 #endif // ILANG_VTARGET_OUT_VTARGET_GEN_JASPER_H__
virtual void PreExportProcess() override
Pre export work : nothing for cosa.
Definition: vtarget_gen_jasper.h:101
virtual void add_an_assertion(const std::string &asst, const std::string &dspt) override
Add an assertion.
std::string jg_script_name
Name of the problem file.
Definition: vtarget_gen_jasper.h:70
void add_addition_clock_info(const std::string &expr)
Verilog Verification Target Generator – for JasperGold Unlike for cosa, we don&#39;t need a separate file...
Definition: vtarget_gen_jasper.h:14
virtual void add_an_assumption(const std::string &aspt, const std::string &dspt) override
Add an assumption.
virtual void add_a_direct_assertion(const std::string &asst, const std::string &dspt) override
Add a direct assertion.
struct ilang::VlgVerifTgtGenBase::_adv_parameters advanced_parameters_t
virtual void Export_script(const std::string &script_name) override
export the script to run the verification
virtual void add_wire_assign_assumption(const std::string &varname, const std::string &expression, const std::string &dspt) override
backend_selector
Definition: vtarget_gen.h:31
Instr::InstrPtr InstrPtr
Pointer type for normal use of Instr.
Definition: instr.h:132
the structure to configure the verilog generator
Definition: verilog_gen.h:150
std::vector< std::string > additional_reset_expr
vector of clock signals that need to be taken care of
Definition: vtarget_gen_jasper.h:68
std::vector< std::string > additional_clock_expr
vector of clock signals that need to be taken care of
Definition: vtarget_gen_jasper.h:65
target_type_t
Type of the target.
Definition: vtarget_gen_impl.h:40
std::string abs_mem_name
Name of the problem file.
Definition: vtarget_gen_jasper.h:72
Generating a target (just the invairant or for an instruction)
Definition: vtarget_gen_impl.h:36
the class to hold supplementary information
Definition: supplementary_info.h:16
virtual void add_a_direct_assumption(const std::string &aspt, const std::string &dspt) override
Add a direct assumption.
InstrLvlAbs::InstrLvlAbsPtr InstrLvlAbsPtr
Pointer type for normal use of InstrLvlAbs.
Definition: instr_lvl_abs.h:326
virtual void add_reg_cassign_assumption(const std::string &varname, const std::string &expression, int width, const std::string &cond, const std::string &dspt) override
std::vector< std::pair< std::string, std::string > > assertions
vector of pairs of &lt;assertions, description&gt;
Definition: vtarget_gen_jasper.h:62
virtual void do_not_instantiate(void) override
It is okay to instantiation.
Definition: vtarget_gen_jasper.h:116
std::vector< std::pair< std::string, std::string > > assumptions
Definition: vtarget_gen_jasper.h:60
virtual void Export_modify_verilog() override
For jasper, this means do nothing, for yosys, you need to add (keep)
The class that invoke the analyzer.
Definition: verilog_analysis_wrapper.h:173
Verilog Target Generation Configuration.
Definition: vtarget_gen.h:55
virtual void Export_mem(const std::string &mem_name) override
Definition: vtarget_gen.h:275
VlgSglTgtGen_Jasper(const std::string &output_path, const InstrPtr &instr_ptr, const InstrLvlAbsPtr &ila_ptr, const VerilogGenerator::VlgGenConfig &config, nlohmann::json &_rf_vmap, nlohmann::json &_rf_cond, VlgTgtSupplementaryInfo &_supplementary_info, VerilogInfo *_vlg_info_ptr, const std::string &vlg_mod_inst_name, const std::string &ila_mod_inst_name, const std::string &wrapper_name, const std::vector< std::string > &implementation_srcs, const std::vector< std::string > &include_dirs, const vtg_config_t &vtg_config, backend_selector backend, const target_type_t &target_tp, advanced_parameters_t *adv_ptr)
virtual void Export_problem(const std::string &extra_name) override
export extra things (problem)