the structure to configure the verilog generator More...

Public Types
enum	funcOption { Internal, External }
	whether to treat function as internal module/external module

Public Member Functions
	VlgGenConfig (bool ExternalMem=true, funcOption funcOpt=funcOption::Internal, bool gen_start=false, bool pass_name=false, bool rand_init=false, bool ExpandMem=false, bool CollectIteUnknownUpdate=false)

	VlgGenConfig (const VlgGenConfig &c, bool ExternalMem, funcOption funcOpt, bool gen_start, bool rand_init, bool ExpandMem, bool CollectIteUnknownUpdate)
	Overwrite configuration, used by vtarget gen.

Public Attributes
bool	extMem

enum ilang::VerilogGeneratorBase::VlgGenConfig::funcOption	fcOpt

bool	start_signal
	whether to have the start signal

bool	pass_node_name
	whether to set vlg name according to the node name

bool	reg_random_init
	whether to give random init to the register

bool	expand_mem

bool	collect_ite_unknown_update
	whether to collect the ite(c, v, unknown) thing

Detailed Description

the structure to configure the verilog generator

Constructor & Destructor Documentation

ilang::VerilogGeneratorBase::VlgGenConfig::VlgGenConfig	(	bool	ExternalMem = `true`,
		funcOption	funcOpt = `funcOption::Internal`,
		bool	gen_start = `false`,
		bool	pass_name = `false`,
		bool	rand_init = `false`,
		bool	ExpandMem = `false`,
		bool	CollectIteUnknownUpdate = `false`
	)

inline

Constructor, set default value, ExternalMem : false, function: internal module

bool ilang::VerilogGeneratorBase::VlgGenConfig::expand_mem

whether to expand the memory and connect everything to the outside cannot be true the same time as extMem

bool ilang::VerilogGeneratorBase::VlgGenConfig::extMem

whether to export as a verilog array or an interface to operate external memory

The documentation for this struct was generated from the following file: