ilasynth::VerilogExport Class Reference

#include <VerilogExport.hpp>

Public Types
typedef std::unordered_map< const Node *, vlg_name_t, decltype(&nodeHash), decltype(&nodeEqual)>	vexpr_map_t

Public Member Functions
	VerilogExport (const std::string &modName, const std::string &clk, const std::string &rst, const VlgExportConfig &config)
void	exportInp (const std::string &name, const npair_t &np)
void	exportReg (const std::string &name, const npair_t &np)
void	exportBit (const std::string &name, const npair_t &np)
void	finalExport (std::ostream &)
void	exportMem (const std::string &name, const npair_t &np)
void	exportFunc (const std::string &name, const npair_t &np)
void	setModuleName (const std::string &modName)
void	exportUabs (const Abstraction &uabs)

Protected Member Functions
int	get_width (const Node *n)
void	add_input (const vlg_name_t &n, int w)
void	add_output (const vlg_name_t &n, int w)
void	add_wire (const vlg_name_t &n, int w)
void	add_reg (const vlg_name_t &n, int w)
void	add_mem (const vlg_name_t &n, int addr_width, int data_width)
void	add_stmt (const vlg_stmt_t &s)
void	add_always_stmt (const vlg_stmt_t &s)
void	add_init_stmt (const vlg_stmt_t &s)
void	add_ite_stmt (const vlg_stmt_t &cond, const vlg_stmt_t &tstmt, const vlg_stmt_t &fstmt)
void	start_iterate (const Node *n)
vlg_name_t	getName (const Node *n)
vlg_name_t	getArg (const Node *n, int i)
vlg_name_t	translateBoolOp (const BoolOp *boolop)
vlg_name_t	translateBitvectorOp (const BitvectorOp *bvop)
void	nodeVistorFunc (const Node *n)
void	exportCondWrites (const std::string &n, int addr_width, int data_width, const mem_write_list_t &writeList)
void	checkMemVar (const Node *n, const MemVar *&mem, int &fail)
void	visitMemNodes (const Node *n, const nptr_t &cond, mem_write_entry_list_stack_t &writesStack)
vlg_name_t	NewId ()
vlg_name_t	NewId (const std::string &refName)

Static Protected Member Functions
static nptr_t	logicalAnd (const nptr_t &c1, const nptr_t &c2)

Protected Attributes
unsigned	idCounter
bool	ExternalMem
bool	FunctionAsModule

Private Member Functions
std::string	WidthToRange (int w)

Private Attributes
vlg_name_t	moduleName
vlg_name_t	clkName
vlg_name_t	rstName
vlg_sigs_t	inputs
vlg_sigs_t	outputs
vlg_sigs_t	mem_i
vlg_sigs_t	mem_o
vlg_sigs_t	wires
vlg_sigs_t	regs
vlg_mems_t	mems
vlg_stmts_t	init_stmts
vlg_stmts_t	statements
vlg_stmts_t	always_stmts
vlg_ite_stmts_t	ite_stmts
vlg_stmt_t	preheader
vexpr_map_t	nmap
rwmap_t	notCache
mem_write_list_t	current_writes
mem_write_list_t	past_writes

Member Typedef Documentation

vexpr_map_t

typedef std::unordered_map<const Node*, vlg_name_t, decltype(&nodeHash), decltype(&nodeEqual)> ilasynth::VerilogExport::vexpr_map_t

Constructor & Destructor Documentation

VerilogExport()

ilasynth::VerilogExport::VerilogExport	(	const std::string &	modName,
		const std::string &	clk,
		const std::string &	rst,
		const VlgExportConfig &	config
	)

Member Function Documentation

add_always_stmt()

void ilasynth::VerilogExport::add_always_stmt ( const vlg_stmt_t &  s )

protected

add_init_stmt()

void ilasynth::VerilogExport::add_init_stmt ( const vlg_stmt_t &  s )

protected

add_input()

void ilasynth::VerilogExport::add_input ( const vlg_name_t &  n, int  w  )

protected

add_ite_stmt()

void ilasynth::VerilogExport::add_ite_stmt ( const vlg_stmt_t &  cond, const vlg_stmt_t &  tstmt, const vlg_stmt_t &  fstmt  )

protected

add_mem()

void ilasynth::VerilogExport::add_mem ( const vlg_name_t &  n, int  addr_width, int  data_width  )

protected

add_output()

void ilasynth::VerilogExport::add_output ( const vlg_name_t &  n, int  w  )

protected

add_reg()

void ilasynth::VerilogExport::add_reg ( const vlg_name_t &  n, int  w  )

protected

add_stmt()

void ilasynth::VerilogExport::add_stmt ( const vlg_stmt_t &  s )

protected

add_wire()

void ilasynth::VerilogExport::add_wire ( const vlg_name_t &  n, int  w  )

protected

checkMemVar()

void ilasynth::VerilogExport::checkMemVar ( const Node *  n, const MemVar *&  mem, int &  fail  )

protected

exportBit()

void ilasynth::VerilogExport::exportBit	(	const std::string &	name,
		const npair_t &	np
	)

exportCondWrites()

void ilasynth::VerilogExport::exportCondWrites ( const std::string &  n, int  addr_width, int  data_width, const mem_write_list_t &  writeList  )

protected

exportFunc()

void ilasynth::VerilogExport::exportFunc	(	const std::string &	name,
		const npair_t &	np
	)

exportInp()

void ilasynth::VerilogExport::exportInp	(	const std::string &	name,
		const npair_t &	np
	)

exportMem()

void ilasynth::VerilogExport::exportMem	(	const std::string &	name,
		const npair_t &	np
	)

exportReg()

void ilasynth::VerilogExport::exportReg	(	const std::string &	name,
		const npair_t &	np
	)

exportUabs()

void ilasynth::VerilogExport::exportUabs ( const Abstraction &  uabs )

inline

finalExport()

void ilasynth::VerilogExport::finalExport

(

std::ostream &

)

get_width()

int ilasynth::VerilogExport::get_width ( const Node *  n )

protected

getArg()

vlg_name_t ilasynth::VerilogExport::getArg ( const Node *  n, int  i  )

protected

getName()

vlg_name_t ilasynth::VerilogExport::getName ( const Node *  n )

protected

logicalAnd()

static nptr_t ilasynth::VerilogExport::logicalAnd ( const nptr_t &  c1, const nptr_t &  c2  )

staticprotected

NewId() [1/2]

vlg_name_t ilasynth::VerilogExport::NewId ( )

protected

NewId() [2/2]

vlg_name_t ilasynth::VerilogExport::NewId ( const std::string &  refName )

protected

nodeVistorFunc()

void ilasynth::VerilogExport::nodeVistorFunc ( const Node *  n )

protected

setModuleName()

void ilasynth::VerilogExport::setModuleName

(

const std::string &

modName

)

start_iterate()

void ilasynth::VerilogExport::start_iterate ( const Node *  n )

protected

translateBitvectorOp()

vlg_name_t ilasynth::VerilogExport::translateBitvectorOp ( const BitvectorOp *  bvop )

protected

translateBoolOp()

vlg_name_t ilasynth::VerilogExport::translateBoolOp ( const BoolOp *  boolop )

protected

visitMemNodes()

void ilasynth::VerilogExport::visitMemNodes ( const Node *  n, const nptr_t &  cond, mem_write_entry_list_stack_t &  writesStack  )

protected

WidthToRange()

std::string ilasynth::VerilogExport::WidthToRange ( int  w )

private

Member Data Documentation

always_stmts

vlg_stmts_t ilasynth::VerilogExport::always_stmts

private

clkName

vlg_name_t ilasynth::VerilogExport::clkName

private

current_writes

mem_write_list_t ilasynth::VerilogExport::current_writes

private

ExternalMem

bool ilasynth::VerilogExport::ExternalMem

protected

FunctionAsModule

bool ilasynth::VerilogExport::FunctionAsModule

protected

idCounter

unsigned ilasynth::VerilogExport::idCounter

protected

init_stmts

vlg_stmts_t ilasynth::VerilogExport::init_stmts

private

inputs

vlg_sigs_t ilasynth::VerilogExport::inputs

private

ite_stmts

vlg_ite_stmts_t ilasynth::VerilogExport::ite_stmts

private

mem_i

vlg_sigs_t ilasynth::VerilogExport::mem_i

private

mem_o

vlg_sigs_t ilasynth::VerilogExport::mem_o

private

mems

vlg_mems_t ilasynth::VerilogExport::mems

private

moduleName

vlg_name_t ilasynth::VerilogExport::moduleName

private

nmap

vexpr_map_t ilasynth::VerilogExport::nmap

private

notCache

rwmap_t ilasynth::VerilogExport::notCache

private

outputs

vlg_sigs_t ilasynth::VerilogExport::outputs

private

past_writes

mem_write_list_t ilasynth::VerilogExport::past_writes

private

preheader

vlg_stmt_t ilasynth::VerilogExport::preheader

private

regs

vlg_sigs_t ilasynth::VerilogExport::regs

private

rstName

vlg_name_t ilasynth::VerilogExport::rstName

private

statements

vlg_stmts_t ilasynth::VerilogExport::statements

private

wires

vlg_sigs_t ilasynth::VerilogExport::wires

private

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The documentation for this class was generated from the following file:

• VerilogExport.hpp