| check_hierarchical_name_type(const std::string &net_name) const | ilang::VerilogAnalyzer | |
| check_resolve_modules(verilog_source_tree *source) | ilang::VerilogAnalyzer | protected |
| create_module_submodule_map(verilog_source_tree *source) | ilang::VerilogAnalyzer | protected |
| find_declaration_of_name(const std::string &net_name) const | ilang::VerilogAnalyzer | |
| find_definition_of_a_module(const std::string &module_name) const | ilang::VerilogAnalyzer | |
| find_definition_of_signal(const std::string &net_name) const | ilang::VerilogAnalyzer | |
| find_top_module(verilog_source_tree *source, const std::string &optional_top_module) | ilang::VerilogAnalyzer | protected |
| get_endmodule_loc(const std::string &inst_name) const | ilang::VerilogAnalyzer | |
| get_hierarchy_from_full_name(const std::string &full_name, VerilogConstantExprEval::param_def_hierarchy &hier, ast_module_declaration **lowest_level) const | ilang::VerilogAnalyzer | |
| get_module_inst_loc(const std::string &inst_name) const | ilang::VerilogAnalyzer | |
| get_module_name_of_net_name(const std::string &net_name) const | ilang::VerilogAnalyzer | |
| get_signal(const std::string &net_name, const std::map< std::string, int > *const width_info=NULL) const | ilang::VerilogAnalyzer | |
| get_top_module_io(const std::map< std::string, int > *const width_info=NULL) const | ilang::VerilogAnalyzer | |
| get_top_module_name() const | ilang::VerilogAnalyzer | inline |
| hierarchical_name_type typedef | ilang::VerilogAnalyzer | |
| I_WIRE_w_INTERNAL_DEF enum value (defined in ilang::VerilogAnalyzerBase) | ilang::VerilogAnalyzerBase | |
| I_WIRE_wo_INTERNAL_DEF enum value (defined in ilang::VerilogAnalyzerBase) | ilang::VerilogAnalyzerBase | |
| in_bad_state() const | ilang::VerilogAnalyzer | inline |
| instance_count | ilang::VerilogAnalyzer | protectedstatic |
| invoke_parser() | ilang::VerilogAnalyzer | protected |
| IO_WIRE_w_INTERNAL_DEF enum value (defined in ilang::VerilogAnalyzerBase) | ilang::VerilogAnalyzerBase | |
| IO_WIRE_wo_INTERNAL_DEF enum value (defined in ilang::VerilogAnalyzerBase) | ilang::VerilogAnalyzerBase | |
| is_input(hierarchical_name_type tp_) | ilang::VerilogAnalyzerBase | inlinestatic |
| is_io_sig(hierarchical_name_type tp_) | ilang::VerilogAnalyzerBase | inlinestatic |
| is_module(hierarchical_name_type tp_) | ilang::VerilogAnalyzerBase | inlinestatic |
| is_output(hierarchical_name_type tp_) | ilang::VerilogAnalyzerBase | inlinestatic |
| is_reg(hierarchical_name_type tp_) | ilang::VerilogAnalyzerBase | inlinestatic |
| is_wire(hierarchical_name_type tp_) | ilang::VerilogAnalyzerBase | inlinestatic |
| Meta2Loc(const ast_metadata &md) | ilang::VerilogAnalyzer | inlinestatic |
| mod_inst_ast_t typedef | ilang::VerilogAnalyzer | |
| mod_inst_t typedef | ilang::VerilogAnalyzer | |
| MODULE enum value (defined in ilang::VerilogAnalyzerBase) | ilang::VerilogAnalyzerBase | |
| module_io_vec_t typedef | ilang::VerilogAnalyzer | |
| module_to_whereuses_map | ilang::VerilogAnalyzer | protected |
| modules_to_submodule_inst_ast_map | ilang::VerilogAnalyzer | protected |
| modules_to_submodules_map | ilang::VerilogAnalyzer | protected |
| name2loc(const std::string &net_name) const | ilang::VerilogAnalyzer | |
| name_decl_buffer_t typedef | ilang::VerilogAnalyzer | |
| name_insts_ast_map_t typedef | ilang::VerilogAnalyzer | |
| name_insts_map_t typedef | ilang::VerilogAnalyzer | |
| name_module_ast_map_t typedef | ilang::VerilogAnalyzer | |
| name_module_map | ilang::VerilogAnalyzer | protected |
| name_names_map_t typedef | ilang::VerilogAnalyzer | |
| name_type_buffer_t typedef | ilang::VerilogAnalyzer | |
| no_internal_def(hierarchical_name_type tp_) | ilang::VerilogAnalyzerBase | inlinestatic |
| NONE enum value (defined in ilang::VerilogAnalyzerBase) | ilang::VerilogAnalyzerBase | |
| O_REG_w_INTERNAL_DEF enum value (defined in ilang::VerilogAnalyzerBase) | ilang::VerilogAnalyzerBase | |
| O_REG_wo_INTERNAL_DEF enum value (defined in ilang::VerilogAnalyzerBase) | ilang::VerilogAnalyzerBase | |
| O_WIRE_w_INTERNAL_DEF enum value (defined in ilang::VerilogAnalyzerBase) | ilang::VerilogAnalyzerBase | |
| O_WIRE_wo_INTERNAL_DEF enum value (defined in ilang::VerilogAnalyzerBase) | ilang::VerilogAnalyzerBase | |
| OTHERS enum value (defined in ilang::VerilogAnalyzerBase) | ilang::VerilogAnalyzerBase | |
| path_vec_t typedef | ilang::VerilogAnalyzer | |
| PrintLoc(std::ostream &os, const vlg_loc_t &loc) | ilang::VerilogAnalyzerBase | inlinestatic |
| PrintMeta(std::ostream &os, const ast_metadata &md) | ilang::VerilogAnalyzer | inlinestatic |
| PrintMetaAst(std::ostream &os, const T *n) | ilang::VerilogAnalyzer | inlinestatic |
| REG enum value (defined in ilang::VerilogAnalyzerBase) | ilang::VerilogAnalyzerBase | |
| top_inst_name | ilang::VerilogAnalyzer | protected |
| top_module_name | ilang::VerilogAnalyzer | protected |
| VerilogAnalyzer(const path_vec_t &include_path, const path_vec_t &srcs, const std::string &top_module_inst_name, const std::string &optional_top_module) | ilang::VerilogAnalyzer | |
| VerilogAnalyzerBase() | ilang::VerilogAnalyzerBase | inline |
| vlg_include_path | ilang::VerilogAnalyzer | protected |
| vlg_loc_t typedef | ilang::VerilogAnalyzer | |
| vlg_src_files | ilang::VerilogAnalyzer | protected |
| WIRE enum value (defined in ilang::VerilogAnalyzerBase) | ilang::VerilogAnalyzerBase | |
| ~VerilogAnalyzer() | ilang::VerilogAnalyzer | |
| ~VerilogAnalyzerBase() | ilang::VerilogAnalyzerBase | inlinevirtual |
1.8.5
