VerilogAnalyzerBase should never be instantiated, only used as a pointer type in class VerilogInfo. More...

Inheritance diagram for ilang::VerilogAnalyzerBase:

Public Types
enum	hierarchical_name_type { NONE = 0, MODULE, I_WIRE_wo_INTERNAL_DEF, O_WIRE_wo_INTERNAL_DEF, IO_WIRE_wo_INTERNAL_DEF, I_WIRE_w_INTERNAL_DEF, O_WIRE_w_INTERNAL_DEF, IO_WIRE_w_INTERNAL_DEF, O_REG_wo_INTERNAL_DEF, O_REG_w_INTERNAL_DEF, REG, WIRE, OTHERS }
	The result of querying a name (please don't change the order of them)

typedef std::vector< std::string >	path_vec_t
	type to store multiple paths

typedef std::pair< std::string, long >	vlg_loc_t
	filename, line number pair : location type

typedef std::map< std::string, std::vector< std::string > >	name_names_map_t
	A map of name -> names.

typedef std::map< std::string, std::string >	mod_inst_t
	type of modulename instance name : instance_name->module_name

typedef std::map< std::string, mod_inst_t >	name_insts_map_t
	A map of module name -> instantiation.

typedef std::map< std::string, hierarchical_name_type >	name_type_buffer_t
	hierarchical name -> hierarchical_name_type map

typedef std::map< std::string, void * >	name_decl_buffer_t
	hierarchical name -> declaration pointer

typedef std::map< std::string, SignalInfoBase >	module_io_vec_t
	Top module signal list.

Static Public Member Functions
static bool	is_reg (hierarchical_name_type tp_)
	decide if a type is a register (port w or wo internal def / internal)

static bool	is_wire (hierarchical_name_type tp_)
	decide if the type is a wire (port w or wo internal def / internal)

static bool	no_internal_def (hierarchical_name_type tp_)
	decide if a type has no internal def

static bool	is_module (hierarchical_name_type tp_)
	decide if a type is module

static bool	is_io_sig (hierarchical_name_type tp_)
	decide if it is port signal

static bool	is_input (hierarchical_name_type tp_)
	decide if it is input signal

static bool	is_output (hierarchical_name_type tp_)
	decide if it is output signal

static std::ostream &	PrintLoc (std::ostream &os, const vlg_loc_t &loc)
	Print location info.

Detailed Description

VerilogAnalyzerBase should never be instantiated, only used as a pointer type in class VerilogInfo.

The documentation for this class was generated from the following file:

Public Types