ilang::VerilogAnalyzer Class Reference

Class for Verilog analysis. More...

#include <verilog_analysis.h>

Inheritance diagram for ilang::VerilogAnalyzer:

Public Types
using	path_vec_t = VerilogAnalyzerBase::path_vec_t
	type to store multiple paths
using	vlg_loc_t = VerilogAnalyzerBase::vlg_loc_t
	filename, line number pair : location type
typedef std::map< std::string, ast_module_declaration * >	name_module_ast_map_t
	A map to find module ast faster.
using	name_names_map_t = VerilogAnalyzerBase::name_names_map_t
	A map of name -> names.
using	mod_inst_t = VerilogAnalyzerBase::mod_inst_t
	type of modulename instance name : instance_name->module_name
using	name_insts_map_t = VerilogAnalyzerBase::name_insts_map_t
	A map of module name -> instantiation.
using	hierarchical_name_type = VerilogAnalyzerBase::hierarchical_name_type
	The result of querying a name (please don't change the order of them)
using	name_type_buffer_t = VerilogAnalyzerBase::name_type_buffer_t
	hierarchical name -> hierarchical_name_type map
using	name_decl_buffer_t = VerilogAnalyzerBase::name_decl_buffer_t
	hierarchical name -> declaration pointer
using	module_io_vec_t = VerilogAnalyzerBase::module_io_vec_t
	Top module signal list.
typedef std::map< std::string, ast_module_instantiation * >	mod_inst_ast_t
	type of instance_name -> instance_ast_node
typedef std::map< std::string, mod_inst_ast_t >	name_insts_ast_map_t
	A map of module name -> the instantiation ast.
Public Types inherited from ilang::VerilogAnalyzerBase
enum	hierarchical_name_type {   NONE = 0, MODULE, I_WIRE_wo_INTERNAL_DEF, O_WIRE_wo_INTERNAL_DEF,   IO_WIRE_wo_INTERNAL_DEF, I_WIRE_w_INTERNAL_DEF, O_WIRE_w_INTERNAL_DEF, IO_WIRE_w_INTERNAL_DEF,   O_REG_wo_INTERNAL_DEF, O_REG_w_INTERNAL_DEF, REG, WIRE,   OTHERS }
	The result of querying a name (please don't change the order of them)
typedef std::vector< std::string >	path_vec_t
	type to store multiple paths
typedef std::pair< std::string, long >	vlg_loc_t
	filename, line number pair : location type
typedef std::map< std::string, std::vector< std::string > >	name_names_map_t
	A map of name -> names.
typedef std::map< std::string, std::string >	mod_inst_t
	type of modulename instance name : instance_name->module_name
typedef std::map< std::string, mod_inst_t >	name_insts_map_t
	A map of module name -> instantiation.
typedef std::map< std::string, hierarchical_name_type >	name_type_buffer_t
	hierarchical name -> hierarchical_name_type map
typedef std::map< std::string, void * >	name_decl_buffer_t
	hierarchical name -> declaration pointer
typedef std::map< std::string, SignalInfoBase >	module_io_vec_t
	Top module signal list.

Public Member Functions
	VerilogAnalyzer (const path_vec_t &include_path, const path_vec_t &srcs, const std::string &top_module_inst_name, const std::string &optional_top_module)
	~VerilogAnalyzer ()
	Destructor: clear vlg parser things.
hierarchical_name_type	check_hierarchical_name_type (const std::string &net_name) const
	Return the type of a name (used externally, cached)
vlg_loc_t	find_definition_of_signal (const std::string &net_name) const
	Return the file location of the definition of a signal.
vlg_loc_t	find_definition_of_a_module (const std::string &module_name) const
	Return the file location of the definition of a module.
void *	find_declaration_of_name (const std::string &net_name) const
vlg_loc_t	name2loc (const std::string &net_name) const
	Return the location of a hierarchical name.
vlg_loc_t	get_module_inst_loc (const std::string &inst_name) const
	Return the location of a module instantiation.
std::string	get_top_module_name () const
	Return top module name.
module_io_vec_t	get_top_module_io (const std::map< std::string, int > *const width_info=NULL) const
	Return top module signal.
SignalInfoBase	get_signal (const std::string &net_name, const std::map< std::string, int > *const width_info=NULL) const
	Find a signal.
vlg_loc_t	get_endmodule_loc (const std::string &inst_name) const
	Return the location of a module's endmodule statement.
std::string	get_module_name_of_net_name (const std::string &net_name) const
	Return the module name of a net — will check if the module names are.
bool	get_hierarchy_from_full_name (const std::string &full_name, VerilogConstantExprEval::param_def_hierarchy &hier, ast_module_declaration **lowest_level) const
bool	in_bad_state () const
	whether this analyzer is in bad state
Public Member Functions inherited from ilang::VerilogAnalyzerBase
	VerilogAnalyzerBase ()
	Constructor: do nothing.
virtual	~VerilogAnalyzerBase ()
	do nothing!

Static Public Member Functions
static std::ostream &	PrintMeta (std::ostream &os, const ast_metadata &md)
	Print Meta info (Usage PrintMeta(os, ?? ) << ?? ; )
template<class T >
static std::ostream &	PrintMetaAst (std::ostream &os, const T *n)
	Print the meta of an Ast node (cannot be void* , has to be converted)
static vlg_loc_t	Meta2Loc (const ast_metadata &md)
	Convert ast_meta to location.
Static Public Member Functions inherited from ilang::VerilogAnalyzerBase
static bool	is_reg (hierarchical_name_type tp_)
	decide if a type is a register (port w or wo internal def / internal)
static bool	is_wire (hierarchical_name_type tp_)
	decide if the type is a wire (port w or wo internal def / internal)
static bool	no_internal_def (hierarchical_name_type tp_)
	decide if a type has no internal def
static bool	is_module (hierarchical_name_type tp_)
	decide if a type is module
static bool	is_io_sig (hierarchical_name_type tp_)
	decide if it is port signal
static bool	is_input (hierarchical_name_type tp_)
	decide if it is input signal
static bool	is_output (hierarchical_name_type tp_)
	decide if it is output signal
static std::ostream &	PrintLoc (std::ostream &os, const vlg_loc_t &loc)
	Print location info.

Protected Member Functions
void	invoke_parser ()
	invoke the parser to parse the files
void	find_top_module (verilog_source_tree *source, const std::string &optional_top_module)
	extract the top module name
void	check_resolve_modules (verilog_source_tree *source)
	check the result of module resolution and update the name_module_map;
void	create_module_submodule_map (verilog_source_tree *source)
	Update the modules_to_submodules_map.

Protected Attributes
path_vec_t	vlg_include_path
	include path for all verilog modules
path_vec_t	vlg_src_files
	verilog source files
std::string	top_module_name
	top module name
name_module_ast_map_t	name_module_map
	a map from name to module ast
name_names_map_t	module_to_whereuses_map
	module -> instantiations
name_insts_map_t	modules_to_submodules_map
	module -> all sub modules
name_insts_ast_map_t	modules_to_submodule_inst_ast_map
	module -> all sub modules and their instantiation ast
std::string	top_inst_name

Static Protected Attributes
static unsigned	instance_count

Detailed Description

Class for Verilog analysis.

Constructor & Destructor Documentation

ilang::VerilogAnalyzer::VerilogAnalyzer	(	const path_vec_t &	include_path,
		const path_vec_t &	srcs,
		const std::string &	top_module_inst_name,
		const std::string &	optional_top_module
	)

Analyze a set of file [in] the path to search for include [in] the source files [in] the instance name given to the topmodule

Member Function Documentation

void* ilang::VerilogAnalyzer::find_declaration_of_name

(

const std::string &

net_name

)

const

Return the declaration of a name, which could be be converted to: ast_module_declaration, ast_net_declaration, ast_reg_declaration, ast_port_declaration

bool ilang::VerilogAnalyzer::get_hierarchy_from_full_name	(	const std::string &	full_name,
		VerilogConstantExprEval::param_def_hierarchy &	hier,
		ast_module_declaration **	lowest_level
	)		const

Get the hierarchy information needed by constant parser returns true if succeed

Member Data Documentation

unsigned ilang::VerilogAnalyzer::instance_count

staticprotected

static instance count, we must make sure there is only one instance of it at a time o.w. it will mess up w. the C code

std::string ilang::VerilogAnalyzer::top_inst_name

protected

we need to know what instance name we would give for the topmodule, inorder to resolve signal names;

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The documentation for this class was generated from the following file:

• verilog_analysis.h