verilog_analysis_wrapper.h

#ifndef ILANG_VERILOG_IN_VERILOG_ANALYSIS_WRAPPER_H__
#define ILANG_VERILOG_IN_VERILOG_ANALYSIS_WRAPPER_H__

#include <iostream>
#include <map>
#include <string>
#include <vector>

namespace ilang {

class SignalInfoBase;

class VerilogAnalyzerBase {
public:
  typedef std::vector<std::string> path_vec_t;
  typedef std::pair<std::string, long> vlg_loc_t;
  typedef std::map<std::string, std::vector<std::string>> name_names_map_t;
  typedef std::map<std::string, std::string> mod_inst_t;
  typedef std::map<std::string, mod_inst_t> name_insts_map_t;
  typedef enum {
    NONE = 0,
    MODULE, /*1*/
    I_WIRE_wo_INTERNAL_DEF,
    /*2*/ // module (input [3:0] a, output reg b) ; no internal defininition
    O_WIRE_wo_INTERNAL_DEF,  /*3*/
    IO_WIRE_wo_INTERNAL_DEF, /*4*/
    I_WIRE_w_INTERNAL_DEF,
    /*5*/ // module (a,b,c); input c **OR** module (input [3:0] a) ; wire [3:0]
          // a;
    O_WIRE_w_INTERNAL_DEF,  /*6*/
    IO_WIRE_w_INTERNAL_DEF, /*7*/
    O_REG_wo_INTERNAL_DEF,  /*8*/
    O_REG_w_INTERNAL_DEF,   /*9*/
    REG /*10*/,
    WIRE /*11*/,
    OTHERS /*12*/
  } hierarchical_name_type;
  typedef std::map<std::string, hierarchical_name_type> name_type_buffer_t;
  typedef std::map<std::string, void*> name_decl_buffer_t;
  typedef std::map<std::string, SignalInfoBase> module_io_vec_t;

public:
  // --------------------- HELPER FUNCTIONS ---------------------------- //
  static bool is_reg(hierarchical_name_type tp_) {
    return tp_ == O_REG_wo_INTERNAL_DEF || tp_ == O_REG_w_INTERNAL_DEF ||
           tp_ == REG;
  }
  static bool is_wire(hierarchical_name_type tp_) {
    return (tp_ >= I_WIRE_wo_INTERNAL_DEF && tp_ <= IO_WIRE_w_INTERNAL_DEF) ||
           tp_ == WIRE;
  }
  static bool no_internal_def(hierarchical_name_type tp_) {
    return (tp_ >= I_WIRE_wo_INTERNAL_DEF && tp_ <= IO_WIRE_wo_INTERNAL_DEF) ||
           tp_ == O_REG_wo_INTERNAL_DEF;
  }
  static bool is_module(hierarchical_name_type tp_) {
    return tp_ == hierarchical_name_type::MODULE;
  }
  static bool is_io_sig(hierarchical_name_type tp_) {
    return tp_ >= I_WIRE_wo_INTERNAL_DEF && tp_ <= O_REG_w_INTERNAL_DEF;
  }
  static bool is_input(hierarchical_name_type tp_) {
    return (tp_ == I_WIRE_wo_INTERNAL_DEF) || (tp_ == I_WIRE_w_INTERNAL_DEF);
  }
  static bool is_output(hierarchical_name_type tp_) {
    return is_io_sig(tp_) && !is_input(tp_);
  }
  static std::ostream& PrintLoc(std::ostream& os, const vlg_loc_t& loc) {
    return (os << (loc.first) << ":" << (loc.second));
  }

public:
  // --------------------- CONSTRUCTOR ---------------------------- //
  VerilogAnalyzerBase(){};
  // --------------------- DESTRUCTOR ---------------------------- //
  virtual ~VerilogAnalyzerBase(){};

};

class SignalInfoBase {
protected:
  const std::string _name;
  const std::string _hierarchical_name;
  const unsigned _width;
  const VerilogAnalyzerBase::hierarchical_name_type _type;
  const VerilogAnalyzerBase::vlg_loc_t _loc;

public:
  virtual unsigned get_width() const { return _width; }
  virtual bool is_io_sig() const {
    return VerilogAnalyzerBase::is_io_sig(_type);
  }
  virtual bool no_internal_def() const {
    return VerilogAnalyzerBase::no_internal_def(_type);
  }
  virtual bool is_reg() const { return VerilogAnalyzerBase::is_reg(_type); }
  virtual bool is_input() const { return VerilogAnalyzerBase::is_input(_type); }
  virtual bool is_output() const {
    return VerilogAnalyzerBase::is_output(_type);
  }
  virtual bool is_bad_signal() const {
    return _type == VerilogAnalyzerBase::hierarchical_name_type::NONE;
  }
  virtual VerilogAnalyzerBase::hierarchical_name_type get_type() const {
    return _type;
  }
  virtual VerilogAnalyzerBase::vlg_loc_t get_decl_loc() const { return _loc; }
  virtual std::string get_signal_name() const { return _name; }
  virtual std::string get_hierarchical_name() const {
    return _hierarchical_name;
  }

public:
  SignalInfoBase(const std::string& n, const std::string& h, unsigned w,
                 const VerilogAnalyzerBase::hierarchical_name_type& typ,
                 const VerilogAnalyzerBase::vlg_loc_t& loc)
      : _name(n), _hierarchical_name(h), _width(w), _type(typ), _loc(loc) {}
}; // class SignalInfoBase

class VerilogInfo {

public:
  using path_vec_t = VerilogAnalyzerBase::path_vec_t;
  using vlg_loc_t = VerilogAnalyzerBase::vlg_loc_t;
  using name_names_map_t = VerilogAnalyzerBase::name_names_map_t;
  using mod_inst_t = VerilogAnalyzerBase::mod_inst_t;
  using name_insts_map_t = VerilogAnalyzerBase::name_insts_map_t;
  using hierarchical_name_type = VerilogAnalyzerBase::hierarchical_name_type;
  using name_type_buffer_t = VerilogAnalyzerBase::name_type_buffer_t;
  using name_decl_buffer_t = VerilogAnalyzerBase::name_decl_buffer_t;
  using module_io_vec_t = VerilogAnalyzerBase::module_io_vec_t;

private:
  // --------------------- MEMBERS ---------------------------- //
  VerilogAnalyzerBase* _analyzer;

public:
  // --------------------- CONSTRUCTOR ---------------------------- //
  VerilogInfo(const path_vec_t& include_path, const path_vec_t& srcs,
              const std::string& top_module_inst_name,
              const std::string& optional_top_module = "");
  VerilogInfo(const VerilogInfo&) = delete;
  VerilogInfo& operator=(const VerilogInfo&) = delete;
  // --------------------- DESTRUCTOR ---------------------------- //
  virtual ~VerilogInfo();

public:
  // --------------------- INTERFACE ---------------------------- //
  hierarchical_name_type
  check_hierarchical_name_type(const std::string& net_name) const;
  void* find_declaration_of_name(const std::string& net_name) const;
  vlg_loc_t name2loc(const std::string& net_name) const;
  vlg_loc_t get_module_inst_loc(const std::string& inst_name) const;
  vlg_loc_t get_endmodule_loc(const std::string& inst_name) const;
  std::string get_top_module_name() const;
  module_io_vec_t get_top_module_io() const;
  module_io_vec_t
  get_top_module_io(const std::map<std::string, int>& width_info) const;
  SignalInfoBase get_signal(const std::string& net_name) const;
  SignalInfoBase get_signal(const std::string& net_name,
                            const std::map<std::string, int>& width_info) const;
  bool in_bad_state() const;

}; // class Verilog Info

std::ostream& operator<<(std::ostream& os,
                         const VerilogAnalyzerBase::vlg_loc_t& obj);

}; // namespace ilang

#endif // ILANG_VERILOG_IN_VERILOG_ANALYSIS_WRAPPER_H__