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vtarget_gen_cosa.h
1 // ---Hongce Zhang
4 
5 #ifndef ILANG_VTARGET_OUT_VTARGET_GEN_COSA_H__
6 #define ILANG_VTARGET_OUT_VTARGET_GEN_COSA_H__
7 
8 #include <ilang/vtarget-out/vlg_mod.h>
9 #include <ilang/vtarget-out/vtarget_gen_impl.h>
10 
11 #include <iostream>
12 #include <string>
13 #include <vector>
14 
15 #include <ilang/config.h>
17 
18 namespace ilang {
19 
20 class VlgSglTgtGen_Cosa;
21 
23 class Cosa_problem {
24  friend class VlgSglTgtGen_Cosa;
26  typedef std::vector<std::string> prop_t;
29  typedef struct {
30  // the name in [??]
31  // std::string problem_name;
33  prop_t assertions;
34  } problem_t;
36  typedef std::map<std::string, problem_t> problemset_t;
37 
38 protected:
40  prop_t assumptions;
42  problemset_t probitem;
43 
44 }; // Cosa_problem
45 
51  using info_t = VerilogModifier::info_t;
53  using fn_l_map_t = VerilogModifier::fn_l_map_t;
56 
57 public:
58  // --------------------- CONSTRUCTOR ---------------------------- //
73  const std::string& output_path, // will be a sub directory of the
74  // output_path of its parent
75  const InstrPtr& instr_ptr, // which could be an empty pointer, and it will
76  // be used to verify invariants
77  const InstrLvlAbsPtr& ila_ptr,
78  const VerilogGenerator::VlgGenConfig& config, nlohmann::json& _rf_vmap,
79  nlohmann::json& _rf_cond, VlgTgtSupplementaryInfo& _supplementary_info,
80  VerilogInfo* _vlg_info_ptr, const std::string& vlg_mod_inst_name,
81  const std::string& ila_mod_inst_name, const std::string& wrapper_name,
82  const std::vector<std::string>& implementation_srcs,
83  const std::vector<std::string>& include_dirs,
84  const vtg_config_t& vtg_config, backend_selector backend,
85  const target_type_t& target_tp, advanced_parameters_t* adv_ptr);
86 
87 protected:
91  std::string cosa_prob_fname;
92 
93 protected:
95  virtual void add_a_direct_assumption(const std::string& aspt,
96  const std::string& dspt) override;
98  virtual void add_a_direct_assertion(const std::string& asst,
99  const std::string& dspt) override;
100 
102  void virtual PreExportProcess() override {}
104  virtual void Export_script(const std::string& script_name) override;
106  virtual void
107  Export_problem(const std::string& extra_name) override; // only for cosa
109  virtual void Export_jg_tester_script(const std::string& extra_name);
110 
114  virtual void Export_mem(const std::string& mem_name) override;
116  virtual void Export_modify_verilog() override;
117 
118 public:
120  virtual void do_not_instantiate(void) override{};
121 
122 }; // class VlgVerifTgtGenCosa
123 
124 }; // namespace ilang
125 
126 #endif // ILANG_VTARGET_OUT_VTARGET_GEN_COSA_H__
virtual void Export_script(const std::string &script_name) override
export the script to run the verification
virtual void PreExportProcess() override
Pre export work : nothing for cosa.
Definition: vtarget_gen_cosa.h:102
a class to store (and generate) the problem for cosa
Definition: vtarget_gen_cosa.h:23
virtual void Export_problem(const std::string &extra_name) override
export extra things (problem)
std::tuple< long, std::string, bool > info_t
a tuple to store all related info for modification
Definition: vlg_mod.h:29
prop_t assumptions
assumptions are shared
Definition: vtarget_gen_cosa.h:40
virtual void Export_modify_verilog() override
For jasper, this means do nothing, for yosys, you need to add (keep)
struct ilang::VlgVerifTgtGenBase::_adv_parameters advanced_parameters_t
virtual void add_a_direct_assertion(const std::string &asst, const std::string &dspt) override
Add a direct assertion.
VlgSglTgtGen_Cosa(const std::string &output_path, const InstrPtr &instr_ptr, const InstrLvlAbsPtr &ila_ptr, const VerilogGenerator::VlgGenConfig &config, nlohmann::json &_rf_vmap, nlohmann::json &_rf_cond, VlgTgtSupplementaryInfo &_supplementary_info, VerilogInfo *_vlg_info_ptr, const std::string &vlg_mod_inst_name, const std::string &ila_mod_inst_name, const std::string &wrapper_name, const std::vector< std::string > &implementation_srcs, const std::vector< std::string > &include_dirs, const vtg_config_t &vtg_config, backend_selector backend, const target_type_t &target_tp, advanced_parameters_t *adv_ptr)
a class to interface w. COSA
Definition: vtarget_gen_cosa.h:47
problemset_t probitem
problems are splitted into items
Definition: vtarget_gen_cosa.h:42
virtual void do_not_instantiate(void) override
It is okay to instantiation.
Definition: vtarget_gen_cosa.h:120
backend_selector
Definition: vtarget_gen.h:31
Instr::InstrPtr InstrPtr
Pointer type for normal use of Instr.
Definition: instr.h:132
the structure to configure the verilog generator
Definition: verilog_gen.h:150
std::string cosa_prob_fname
Cosa problem file name.
Definition: vtarget_gen_cosa.h:91
target_type_t
Type of the target.
Definition: vtarget_gen_impl.h:40
virtual void Export_jg_tester_script(const std::string &extra_name)
generate along-side a jg script that you can use in JasperGold
Generating a target (just the invairant or for an instruction)
Definition: vtarget_gen_impl.h:36
the class to hold supplementary information
Definition: supplementary_info.h:16
std::map< std::string, std::vector< info_t > > fn_l_map_t
filename -&gt; (lineno, varname, is_port_sig) vec
Definition: vlg_mod.h:33
virtual void add_a_direct_assumption(const std::string &aspt, const std::string &dspt) override
Add a direct assumption.
InstrLvlAbs::InstrLvlAbsPtr InstrLvlAbsPtr
Pointer type for normal use of InstrLvlAbs.
Definition: instr_lvl_abs.h:326
Cosa_problem _problems
Cosa problem generate.
Definition: vtarget_gen_cosa.h:89
virtual void Export_mem(const std::string &mem_name) override
The class that invoke the analyzer.
Definition: verilog_analysis_wrapper.h:173
Verilog Target Generation Configuration.
Definition: vtarget_gen.h:55
Definition: vtarget_gen.h:275