8 #ifndef VTARGET_GEN_RELCHC_H__
9 #define VTARGET_GEN_RELCHC_H__
14 #include <ilang/vtarget-out/vlg_mod.h>
15 #include <ilang/vtarget-out/vtarget_gen_impl.h>
22 class VlgSglTgtGen_Relchc;
28 typedef std::vector<std::string> prop_t;
38 typedef std::map<std::string, problem_t> problemset_t;
76 const std::string& output_path,
83 const std::string& vlg_mod_inst_name,
84 const std::string& ila_mod_inst_name,
const std::string& wrapper_name,
85 const std::vector<std::string>& implementation_srcs,
86 const std::vector<std::string>& include_dirs,
107 const std::string& dspt)
override;
110 const std::string& dspt)
override;
115 virtual void Export_script(
const std::string& script_name)
override;
122 virtual void Export_mem(
const std::string& mem_name)
override;
136 void dual_inv_problem(
const std::string& ys_script_name);
139 void dual_inv_tpl(
const std::string & tpl_name,
const std::string & smt_info);
142 std::string dual_inv_gen_smt(
143 const std::string & smt_name,
144 const std::string & ys_script_name);
150 void virtual ExportAll(
const std::string& wrapper_name,
151 const std::string& ila_vlg_name,
152 const std::string& script_name,
153 const std::string& extra_name,
154 const std::string& mem_name)
override;
165 #endif // VTARGET_GEN_RELCHC_H__
VlgSglTgtGen_Relchc(const std::string &output_path, const InstrPtr &instr_ptr, const InstrLvlAbsPtr &ila_ptr, const VerilogGenerator::VlgGenConfig &config, nlohmann::json &_rf_vmap, nlohmann::json &_rf_cond, VlgTgtSupplementaryInfo &_sup_info, VerilogInfo *_vlg_info_ptr, const std::string &vlg_mod_inst_name, const std::string &ila_mod_inst_name, const std::string &wrapper_name, const std::vector< std::string > &implementation_srcs, const std::vector< std::string > &include_dirs, const vtg_config_t &vtg_config, backend_selector backend, const target_type_t &target_tp, advanced_parameters_t *adv_ptr)
virtual void Export_mem(const std::string &mem_name) override
std::tuple< long, std::string, bool > info_t
a tuple to store all related info for modification
Definition: vlg_mod.h:29
problemset_t assertions
problems are splitted into items
Definition: vtarget_gen_relchc.h:44
struct ilang::VlgVerifTgtGenBase::_adv_parameters advanced_parameters_t
virtual void Export_problem(const std::string &extra_name) override
export extra things: the relchc script, the smt template
std::vector< std::string > vlg_mod_inv_vec
the invariants on the design
Definition: vtarget_gen_relchc.h:102
virtual ~VlgSglTgtGen_Relchc()
Destructor: do nothing , most importantly it is virtual.
Definition: vtarget_gen_relchc.h:92
backend_selector
Definition: vtarget_gen.h:31
virtual void ExportAll(const std::string &wrapper_name, const std::string &ila_vlg_name, const std::string &script_name, const std::string &extra_name, const std::string &mem_name) override
Deprecation of the one without smt info.
std::string relchc_run_script_name
Relchc script 'run.sh' name.
Definition: vtarget_gen_relchc.h:100
Instr::InstrPtr InstrPtr
Pointer type for normal use of Instr.
Definition: instr.h:132
virtual void do_not_instantiate(void) override
It is okay to instantiation.
Definition: vtarget_gen_relchc.h:158
the structure to configure the verilog generator
Definition: verilog_gen.h:150
std::string relchc_prob_fname
Relchc problem file name.
Definition: vtarget_gen_relchc.h:98
target_type_t
Type of the target.
Definition: vtarget_gen_impl.h:40
Generating a target (just the invairant or for an instruction)
Definition: vtarget_gen_impl.h:36
virtual void Export_script(const std::string &script_name) override
export the script to run the verification
the class to hold supplementary information
Definition: supplementary_info.h:16
std::map< std::string, std::vector< info_t > > fn_l_map_t
filename -> (lineno, varname, is_port_sig) vec
Definition: vlg_mod.h:33
InstrLvlAbs::InstrLvlAbsPtr InstrLvlAbsPtr
Pointer type for normal use of InstrLvlAbs.
Definition: instr_lvl_abs.h:326
virtual void Export_modify_verilog() override
For jasper, this means do nothing, for relchc, you need to add (keep)
virtual void add_a_direct_assertion(const std::string &asst, const std::string &dspt) override
Add a direct assertion – needed by base class.
Relchc_problem _problems
Relchc problem generate.
Definition: vtarget_gen_relchc.h:96
virtual void add_a_direct_assumption(const std::string &aspt, const std::string &dspt) override
Add a direct assumption – needed by base class.
The class that invoke the analyzer.
Definition: verilog_analysis_wrapper.h:173
Verilog Target Generation Configuration.
Definition: vtarget_gen.h:55
problemset_t assumptions
assumptions are not shared (unlike CoSA)
Definition: vtarget_gen_relchc.h:42
a class to interface w. Relchc Z3
Definition: vtarget_gen_relchc.h:50
Definition: vtarget_gen.h:275
a class to store (and generate) the problem for Relchc (Z3)
Definition: vtarget_gen_relchc.h:25
virtual void PreExportProcess() override
Pre export work : add assume and asssert to the top level.