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vtarget_gen_relchc.h
1 // ---Hongce Zhang
7 
8 #ifndef VTARGET_GEN_RELCHC_H__
9 #define VTARGET_GEN_RELCHC_H__
10 
11 #include <ilang/config.h>
12 
14 #include <ilang/vtarget-out/vlg_mod.h>
15 #include <ilang/vtarget-out/vtarget_gen_impl.h>
16 #include <iostream>
17 #include <string>
18 #include <vector>
19 
20 namespace ilang {
21 
22 class VlgSglTgtGen_Relchc;
23 
26  friend class VlgSglTgtGen_Relchc;
28  typedef std::vector<std::string> prop_t;
31  typedef struct {
32  // the name in [??]
33  // std::string problem_name;
35  prop_t exprs;
36  } problem_t;
38  typedef std::map<std::string, problem_t> problemset_t;
39 
40 protected:
42  problemset_t assumptions;
44  problemset_t assertions;
45 
46 }; // Relchc_problem
47 
48 
54  using info_t = VerilogModifier::info_t;
56  using fn_l_map_t = VerilogModifier::fn_l_map_t;
59 
60 public:
61  // --------------------- CONSTRUCTOR ---------------------------- //
76  const std::string& output_path, // will be a sub directory of the
77  // output_path of its parent
78  const InstrPtr& instr_ptr, // which could be an empty pointer, and it will
79  // be used to verify invariants
80  const InstrLvlAbsPtr& ila_ptr,
81  const VerilogGenerator::VlgGenConfig& config, nlohmann::json& _rf_vmap,
82  nlohmann::json& _rf_cond, VlgTgtSupplementaryInfo & _sup_info, VerilogInfo* _vlg_info_ptr,
83  const std::string& vlg_mod_inst_name,
84  const std::string& ila_mod_inst_name, const std::string& wrapper_name,
85  const std::vector<std::string>& implementation_srcs,
86  const std::vector<std::string>& include_dirs,
87  const vtg_config_t& vtg_config, backend_selector backend,
88  const target_type_t& target_tp,
89  advanced_parameters_t * adv_ptr);
90 
92  virtual ~VlgSglTgtGen_Relchc() {}
93 
94 protected:
98  std::string relchc_prob_fname;
102  std::vector<std::string> vlg_mod_inv_vec;
103 
104 protected:
106  virtual void add_a_direct_assumption(const std::string& aspt,
107  const std::string& dspt) override;
109  virtual void add_a_direct_assertion(const std::string& asst,
110  const std::string& dspt) override;
111 
113  void virtual PreExportProcess() override;
115  virtual void Export_script(const std::string& script_name) override;
117  virtual void
118  Export_problem(const std::string& extra_name) override;
122  virtual void Export_mem(const std::string& mem_name) override;
124  virtual void Export_modify_verilog() override;
125 
126 private:
127  // Here begins the specific functions
128  // single_inv_problem() : gensmt.ys
129  // dual_inv_problem() : gensmt.ys
130  // single_inv_script() : same run.sh
131  // dual_inv_script()
132  // single_inv_tpl() :
133  // dual_inv_tpl() :
134 
136  void dual_inv_problem(const std::string& ys_script_name);
137 
139  void dual_inv_tpl(const std::string & tpl_name, const std::string & smt_info);
140 
142  std::string dual_inv_gen_smt(
143  const std::string & smt_name,
144  const std::string & ys_script_name);
145 
146 
147 public:
148 
150  void virtual ExportAll(const std::string& wrapper_name,
151  const std::string& ila_vlg_name,
152  const std::string& script_name,
153  const std::string& extra_name,
154  const std::string& mem_name) override;
155 
156 
158  virtual void do_not_instantiate(void) override { };
159 
160 }; // class VlgVerifTgtGenRelchc
161 
162 
163 }; // namespace ilang
164 
165 #endif // VTARGET_GEN_RELCHC_H__
VlgSglTgtGen_Relchc(const std::string &output_path, const InstrPtr &instr_ptr, const InstrLvlAbsPtr &ila_ptr, const VerilogGenerator::VlgGenConfig &config, nlohmann::json &_rf_vmap, nlohmann::json &_rf_cond, VlgTgtSupplementaryInfo &_sup_info, VerilogInfo *_vlg_info_ptr, const std::string &vlg_mod_inst_name, const std::string &ila_mod_inst_name, const std::string &wrapper_name, const std::vector< std::string > &implementation_srcs, const std::vector< std::string > &include_dirs, const vtg_config_t &vtg_config, backend_selector backend, const target_type_t &target_tp, advanced_parameters_t *adv_ptr)
virtual void Export_mem(const std::string &mem_name) override
std::tuple< long, std::string, bool > info_t
a tuple to store all related info for modification
Definition: vlg_mod.h:29
problemset_t assertions
problems are splitted into items
Definition: vtarget_gen_relchc.h:44
struct ilang::VlgVerifTgtGenBase::_adv_parameters advanced_parameters_t
virtual void Export_problem(const std::string &extra_name) override
export extra things: the relchc script, the smt template
std::vector< std::string > vlg_mod_inv_vec
the invariants on the design
Definition: vtarget_gen_relchc.h:102
virtual ~VlgSglTgtGen_Relchc()
Destructor: do nothing , most importantly it is virtual.
Definition: vtarget_gen_relchc.h:92
backend_selector
Definition: vtarget_gen.h:31
virtual void ExportAll(const std::string &wrapper_name, const std::string &ila_vlg_name, const std::string &script_name, const std::string &extra_name, const std::string &mem_name) override
Deprecation of the one without smt info.
std::string relchc_run_script_name
Relchc script &#39;run.sh&#39; name.
Definition: vtarget_gen_relchc.h:100
Instr::InstrPtr InstrPtr
Pointer type for normal use of Instr.
Definition: instr.h:132
virtual void do_not_instantiate(void) override
It is okay to instantiation.
Definition: vtarget_gen_relchc.h:158
the structure to configure the verilog generator
Definition: verilog_gen.h:150
std::string relchc_prob_fname
Relchc problem file name.
Definition: vtarget_gen_relchc.h:98
target_type_t
Type of the target.
Definition: vtarget_gen_impl.h:40
Generating a target (just the invairant or for an instruction)
Definition: vtarget_gen_impl.h:36
virtual void Export_script(const std::string &script_name) override
export the script to run the verification
the class to hold supplementary information
Definition: supplementary_info.h:16
std::map< std::string, std::vector< info_t > > fn_l_map_t
filename -&gt; (lineno, varname, is_port_sig) vec
Definition: vlg_mod.h:33
InstrLvlAbs::InstrLvlAbsPtr InstrLvlAbsPtr
Pointer type for normal use of InstrLvlAbs.
Definition: instr_lvl_abs.h:326
virtual void Export_modify_verilog() override
For jasper, this means do nothing, for relchc, you need to add (keep)
virtual void add_a_direct_assertion(const std::string &asst, const std::string &dspt) override
Add a direct assertion – needed by base class.
Relchc_problem _problems
Relchc problem generate.
Definition: vtarget_gen_relchc.h:96
virtual void add_a_direct_assumption(const std::string &aspt, const std::string &dspt) override
Add a direct assumption – needed by base class.
The class that invoke the analyzer.
Definition: verilog_analysis_wrapper.h:173
Verilog Target Generation Configuration.
Definition: vtarget_gen.h:55
problemset_t assumptions
assumptions are not shared (unlike CoSA)
Definition: vtarget_gen_relchc.h:42
a class to interface w. Relchc Z3
Definition: vtarget_gen_relchc.h:50
Definition: vtarget_gen.h:275
a class to store (and generate) the problem for Relchc (Z3)
Definition: vtarget_gen_relchc.h:25
virtual void PreExportProcess() override
Pre export work : add assume and asssert to the top level.