absmem.h

// --- Hongce Zhang

#ifndef ILANG_VTARGET_OUT_ABS_MEM_H__
#define ILANG_VTARGET_OUT_ABS_MEM_H__

#include <map>
#include <set>
#include <string>
#include <tuple>
#include <vector>

#include <ilang/verilog-out/verilog_gen.h>
#include <ilang/vtarget-out/absmem.h>

namespace ilang {

struct VlgAbsMem {
  // ---------------------- TYPES --------------- //
  using rport_t = VerilogGeneratorBase::rport_t;
  using wport_t = VerilogGeneratorBase::wport_t;

  // ---------------------- MEMBERS --------------- //
  std::map<unsigned, rport_t> vlg_rports;
  std::map<unsigned, wport_t> vlg_wports;
  std::map<unsigned, rport_t> ila_rports;
  std::map<unsigned, wport_t> ila_wports;

  bool read_abstract;
  unsigned concrete_level;
  unsigned data_width;
  unsigned addr_width;
  std::string ila_map_name;
  std::string mem_name;
  std::vector<std::string> assumpts;

private:
  bool checked;
  static std::set<int> concrete_level_encountered;

public:
  // ------------------CONSTRUCTOR ----------- //
  VlgAbsMem();
  // ------------------ MEMBERS ------------- //
  void SetAddrWidth(unsigned w);
  void SetDataWidth(unsigned w);
  std::string MemEQSignalName() const;
  std::string
  GeneratingMemModuleSignalsInstantiation(VerilogGeneratorBase& gen,
                                          const std::string& endCond);
  static void OutputMemFile(std::ostream& os, bool avoid_issue_stage);
  static bool hasAbsMem();
  static void ClearAbsMemRecord();

}; // class VlgAbsMem

}; // namespace ilang

#endif // ILANG_VTARGET_OUT_ABS_MEM_H__