a struct to store abstract memory More...

#include <absmem.h>

Public Types
using	rport_t = VerilogGeneratorBase::rport_t
	type of read port

using	wport_t = VerilogGeneratorBase::wport_t
	type of write port

Public Member Functions
	VlgAbsMem ()
	do nothing

void	SetAddrWidth (unsigned w)
	SetAddrWidth, if already set, and different -> error.

void	SetDataWidth (unsigned w)
	SetDataWidth.

std::string	MemEQSignalName () const
	Get the memeq signal name.

std::string	GeneratingMemModuleSignalsInstantiation (VerilogGeneratorBase &gen, const std::string &endCond)

Static Public Member Functions
static void	OutputMemFile (std::ostream &os, bool avoid_issue_stage)
	Output the memory module to the stream.

static bool	hasAbsMem ()
	Return true if there are abs mem used (strategy : ALL -> AUTO)

static void	ClearAbsMemRecord ()
	reset concrete_level (per-target).

Public Attributes
std::map< unsigned, rport_t >	vlg_rports
	verilog read ports

std::map< unsigned, wport_t >	vlg_wports
	verilog write ports

std::map< unsigned, rport_t >	ila_rports
	ila read ports

std::map< unsigned, wport_t >	ila_wports
	ila write ports

bool	read_abstract
	whether to abstract the memory read

unsigned	concrete_level
	how many are considered to be concrete

unsigned	data_width
	widths , 0 stands for unknown

unsigned	addr_width
	widths , 0 stands for unknown

std::string	ila_map_name
	which ila state it is mapped to

std::string	mem_name
	the name in rfmap

std::vector< std::string >	assumpts
	the assumptions it has

Detailed Description

a struct to store abstract memory

Member Function Documentation

std::string ilang::VlgAbsMem::GeneratingMemModuleSignalsInstantiation	(	VerilogGeneratorBase &	gen,
		const std::string &	endCond
	)

Get the memory module instantiation string, it will also add signals when necessary

The documentation for this struct was generated from the following file: