ilang
1.1.4
ILAng: A Modeling and Verification Platform for SoCs
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#include <list>
#include <map>
#include <unordered_map>
#include <vector>
#include <ilang/ila/instr_lvl_abs.h>
Go to the source code of this file.
Classes | |
class | ilang::VerilogGeneratorBase |
Base class of VerilogGenerator. More... | |
struct | ilang::VerilogGeneratorBase::rport_t |
type of read port More... | |
struct | ilang::VerilogGeneratorBase::wport_t |
type of write port More... | |
struct | ilang::VerilogGeneratorBase::mem_write_entry_t |
This is type of an individual write. More... | |
struct | ilang::VerilogGeneratorBase::mem_write_t |
This is the write and its associated condition. More... | |
struct | ilang::VerilogGeneratorBase::function_app_t |
Type of app func. More... | |
struct | ilang::VerilogGeneratorBase::state_update_unknown |
Type of ite update unknown. More... | |
struct | ilang::VerilogGeneratorBase::VlgGenConfig |
the structure to configure the verilog generator More... | |
class | ilang::VerilogGenerator |
Class of Verilog Generator. More... | |
Namespaces | |
ilang | |
Typedefs | |
typedef ExprHash | ilang::VerilogGenHash |
Header for generating Verilog files Currently not supported
For 0-ary func, they will be treated as nondet apply the same nondet func twice, will generate two variables if you do want to share the nondet val, please reuse the sub-tree