verilog_gen.h

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#ifndef ILANG_VERILOG_OUT_VERILOG_GEN_H__
#define ILANG_VERILOG_OUT_VERILOG_GEN_H__

#include <list>
#include <map>
#include <unordered_map>
#include <vector>

#include <ilang/ila/instr_lvl_abs.h>

namespace ilang {

typedef ExprHash VerilogGenHash;
class VlgSglTgtGen;
class VlgVerifTgtGen;
class IntefaceDirectiveRecorder;
class TestVerilogExport;

class VerilogGeneratorBase {
public:
  // --------------------- TYPE DEFINITIONS ---------------------------- //
  using IlaBoolValType = bool;
  using IlaBvValType = BvVal::BvValType;
  using IlaBvValUnsignedType = BvVal::BvValType;
  friend class TestVerilogExport;
  friend class VlgSglTgtGen;
  friend class IntefaceDirectiveRecorder;
  typedef struct {
    std::string raddr;
    std::string rdata;
    std::string ren;
  } rport_t;
  typedef struct {
    std::string waddr;
    std::string wdata;
    std::string wen;
  } wport_t;

  typedef std::string vlg_name_t;
  typedef std::string vlg_stmt_t;
  typedef std::string vlg_const_t;
  typedef std::string vlg_addr_t;
  typedef std::string vlg_data_t;
  typedef std::vector<vlg_name_t> vlg_stmts_t;
  typedef std::vector<vlg_name_t> vlg_names_t;
  typedef std::pair<vlg_name_t, int> vlg_sig_t;
  typedef std::vector<vlg_sig_t> vlg_sigs_t;
  typedef std::map<vlg_name_t, int> vlg_sigs_map_t;
  typedef std::map<vlg_name_t, bool> vlg_sig_keep_t;
  typedef std::set<vlg_sig_t> vlg_sigs_set_t;
  typedef std::tuple<vlg_stmt_t, vlg_stmt_t, vlg_stmt_t> vlg_ite_stmt_t;
  typedef std::vector<vlg_ite_stmt_t> vlg_ite_stmts_t;
  typedef std::tuple<vlg_name_t, int, int, int>
      vlg_mem_t; // name addr_width data_width entryNum
  typedef std::map<vlg_name_t, vlg_mem_t> vlg_mems_rec_t;
  struct mem_write_entry_t {
    ExprPtr addr;
    ExprPtr data;
  };
  typedef std::list<mem_write_entry_t> mem_write_entry_list_t;
  typedef std::list<mem_write_entry_list_t> mem_write_entry_list_stack_t;
  struct mem_write_t {
    ExprPtr cond;
    mem_write_entry_list_t writes;
  };
  typedef std::list<mem_write_t> mem_write_list_t;

  struct function_app_t {
    std::vector<vlg_sig_t> args;
    const vlg_sig_t result;
    const std::string func_name;
    function_app_t(const vlg_sig_t& res, const std::string fn)
        : result(res), func_name(fn) {}
  }; // struct function_app_t
  typedef std::vector<function_app_t> function_app_vec_t;

  struct state_update_unknown {
    const vlg_name_t condition;
    // you don't need the value
    state_update_unknown(const vlg_name_t & c) : condition(c) {}
  }; // struct state_update_unknown
  typedef std::map<std::string, state_update_unknown> state_update_ite_unknown_map_t;

  typedef std::unordered_map<const ExprPtr, vlg_name_t, VerilogGenHash> ExprMap;
  // (this is needed because our hash is not fully working)
  typedef std::map<std::pair<IlaBvValType, unsigned>, vlg_name_t> CnstMap;
  typedef std::map<std::string, bool> memory_export_annotation_t;

  // VerilogGen Configure
public:
  struct VlgGenConfig {
    bool extMem;
    enum funcOption { Internal, External } fcOpt;
    bool start_signal;
    bool pass_node_name;
    bool reg_random_init; // this is also to avoid Yosys optimization
    bool expand_mem;
    bool collect_ite_unknown_update;

    VlgGenConfig( // provide the default settings
        bool ExternalMem = true, funcOption funcOpt = funcOption::Internal,
        bool gen_start = false, bool pass_name = false, bool rand_init = false,
        bool ExpandMem = false, bool CollectIteUnknownUpdate = false)
        : extMem(ExternalMem), fcOpt(funcOpt), start_signal(gen_start),
          pass_node_name(pass_name), reg_random_init(rand_init),
          expand_mem(ExpandMem), collect_ite_unknown_update(CollectIteUnknownUpdate) {}
    VlgGenConfig(const VlgGenConfig& c, bool ExternalMem, funcOption funcOpt,
                 bool gen_start, bool rand_init, bool ExpandMem, bool CollectIteUnknownUpdate)
        : extMem(ExternalMem), fcOpt(funcOpt), start_signal(gen_start),
          pass_node_name(c.pass_node_name), reg_random_init(rand_init),
          expand_mem(ExpandMem), collect_ite_unknown_update(CollectIteUnknownUpdate) {}
    // set other fields if there are such need (?)
  }; // end of struct VlgGenConfig

  // --------------------- HELPER for DEBUG PURPOSE ----------------------------
  //
  friend std::ostream& operator<<(std::ostream& out,
                                  const mem_write_entry_t& mwe);
  friend std::ostream& operator<<(std::ostream& out,
                                  const mem_write_entry_list_t& mwel);
  friend std::ostream& operator<<(std::ostream& out,
                                  const mem_write_entry_list_stack_t& mwel);
  friend std::ostream& operator<<(std::ostream& out, const mem_write_t& mw);
  friend std::ostream& operator<<(std::ostream& out,
                                  const mem_write_list_t& mwl);

  // --------------------- MEMBERS ---------------------------- //
protected:
  // --------------------- Verilog  related ---------------------------- //
  vlg_name_t moduleName;
  vlg_name_t clkName;
  vlg_name_t rstName;
  vlg_names_t decodeNames;
  vlg_name_t validName;
  vlg_name_t startName;
  vlg_sig_t grantAccName;
  vlg_sig_t decodeAccName;
  vlg_name_t counterName;
  vlg_sigs_map_t inputs;
  vlg_sigs_map_t outputs;
  vlg_sigs_t mem_i;
  vlg_sigs_t mem_o;
  vlg_sigs_t mem_probe_o;
  vlg_sigs_map_t wires;
  vlg_sig_keep_t wires_keep;
  vlg_sigs_t regs;
  vlg_mems_rec_t mems_internal;
  vlg_mems_rec_t mems_external;
  vlg_stmts_t init_stmts;
  vlg_stmts_t init_assumpts;
  vlg_stmts_t statements;
  vlg_stmts_t always_stmts;
  vlg_ite_stmts_t
      ite_stmts; // this stmt is only used in sequential always block
  vlg_stmt_t preheader;
  ExprMap nmap;
  CnstMap cmap;

  mem_write_list_t current_writes;
  mem_write_list_t past_writes;

  vlg_sigs_set_t all_valid_names;
  std::map<std::string, std::map<unsigned, rport_t>> ila_rports;
  std::map<std::string, std::map<unsigned, wport_t>> ila_wports;
  function_app_vec_t ila_func_app;
  state_update_ite_unknown_map_t state_update_ite_unknown;
  // Annotations
  memory_export_annotation_t memory_export_annotation;

  // --------------------- HELPER FUNCTIONS ---------------------------- //
  bool check_reserved_name(const vlg_name_t& n) const;
  int static get_width(const ExprPtr& n);
  std::string static WidthToRange(int w);
  vlg_name_t new_id();
  vlg_name_t new_id(const ExprPtr& e);

public:
  static vlg_name_t sanitizeName(const vlg_name_t& n);
  static vlg_name_t sanitizeName(const ExprPtr& n);
  static vlg_const_t ToVlgNum(IlaBvValType value, unsigned width);

protected:
  unsigned idCounter;
  const VlgGenConfig cfg_;
  std::map<std::string, std::string> reference_name_set;
  std::set<FuncPtr> func_ptr_set;

  // --------------------- HELPER FUNCTIONS ---------------------------- //
public:
  void add_input(const vlg_name_t& n, int w);
  void add_output(const vlg_name_t& n, int w);
  void add_wire(const vlg_name_t& n, int w, bool keep = false);
  void add_reg(const vlg_name_t& n, int w);
  void add_stmt(const vlg_stmt_t& s);
  void add_assign_stmt(const vlg_name_t& l, const vlg_name_t& r);
  void add_always_stmt(const vlg_stmt_t& s);
  void add_init_stmt(const vlg_stmt_t& s);
  void add_ite_stmt(const vlg_stmt_t& cond, const vlg_stmt_t& tstmt,
                    const vlg_stmt_t& fstmt);
  void add_internal_mem(const vlg_name_t& mem_name, int addr_width,
                        int data_width, int entry_num);
  void add_external_mem(const vlg_name_t& mem_name, int addr_width,
                        int data_width, int entry_num);
  void add_preheader(const vlg_stmt_t& stmt);

public:
  // --------------------- CONSTRUCTOR ---------------------------- //
  VerilogGeneratorBase(const VlgGenConfig& config = VlgGenConfig(),
                       const std::string& modName = "",
                       const std::string& clk = "clk",
                       const std::string& rst = "rst");

  virtual void DumpToFile(std::ostream& fout) const;

  // --------------------- ANNOTATION INTERFACE ---------------------------- //
  void AnnotateMemory(const memory_export_annotation_t& annotation);
}; // class VerilogGeneratorBase

class VerilogGenerator : public VerilogGeneratorBase {
public:
  // --------------------- TYPE DEFINITIONS ---------------------------- //
  friend class TestVerilogExport;
  using vlg_name_t = VerilogGeneratorBase::vlg_name_t;
  using vlg_stmt_t = VerilogGeneratorBase::vlg_stmt_t;
  using vlg_addr_t = VerilogGeneratorBase::vlg_addr_t;
  using vlg_data_t = VerilogGeneratorBase::vlg_data_t;
  using vlg_stmts_t = VerilogGeneratorBase::vlg_stmts_t;
  using vlg_names_t = VerilogGeneratorBase::vlg_names_t;
  using vlg_sig_t = VerilogGeneratorBase::vlg_sig_t;
  using vlg_sigs_t = VerilogGeneratorBase::vlg_sigs_t;
  using vlg_sig_keep_t = VerilogGeneratorBase::vlg_sig_keep_t;
  using vlg_sigs_set_t = VerilogGeneratorBase::vlg_sigs_set_t;
  using vlg_ite_stmt_t = VerilogGeneratorBase::vlg_ite_stmt_t;
  using vlg_ite_stmts_t = VerilogGeneratorBase::vlg_ite_stmts_t;
  using vlg_mem_t = VerilogGeneratorBase::vlg_mem_t;
  using vlg_mems_rec_t = VerilogGeneratorBase::vlg_mems_rec_t;
  using mem_write_entry_t = VerilogGeneratorBase::mem_write_entry_t;
  using mem_write_entry_list_t = VerilogGeneratorBase::mem_write_entry_list_t;
  using mem_write_entry_list_stack_t =
      VerilogGeneratorBase::mem_write_entry_list_stack_t;
  using mem_write_t = VerilogGeneratorBase::mem_write_t;
  using mem_write_list_t = VerilogGeneratorBase::mem_write_list_t;
  using ExprMap = VerilogGeneratorBase::ExprMap;
  // VerilogGen Configure
  using VlgGenConfig = VerilogGeneratorBase::VlgGenConfig;
  using function_app_t = VerilogGeneratorBase::function_app_t;
  using function_app_vec_t = VerilogGeneratorBase::function_app_vec_t;

private:
  // --------------------- HELPER FUNCTIONS ---------------------------- //
  void insertInput(const ExprPtr& input);
  void insertState(const ExprPtr& state);

  // Here we are not using depthfirstSearch as we need to alternate between
  // root-first/root-last traversal
  void parseArg(const ExprPtr& e);
  VerilogGenerator::vlg_name_t getVlgFromExpr(const ExprPtr& e);
  VerilogGenerator::vlg_name_t getArg(const ExprPtr& e, const size_t& i);
  vlg_name_t translateApplyFunc(std::shared_ptr<ExprOpAppFunc> func_app_ptr_);
  vlg_name_t translateBoolOp(const std::shared_ptr<ExprOp>& e);
  vlg_name_t translateBvOp(const std::shared_ptr<ExprOp>& e);
  void ParseNonMemUpdateExpr(const ExprPtr& e);
  bool CheckMemUpdateNode(const ExprPtr& e, const std::string& mem_var_name);
  void VisitMemNodes(const ExprPtr& e, const ExprPtr& cond,
                     mem_write_entry_list_stack_t& writesStack);

  void addInternalCounter(vlg_name_t decode_sig_name, size_t width = 8);
  void ExportFuncDefs();

  void ExportCondWrites(const ExprPtr& mem_var,
                        const mem_write_list_t& writeList);
  void ParseMemUpdateNode(const ExprPtr& cond, const ExprPtr& e,
                          const std::string& mem_var_name);

public:
  // --------------------- CONSTRUCTOR ---------------------------- //
  VerilogGenerator(const VlgGenConfig& config = VlgGenConfig(),
                   const std::string& modName = "",
                   const std::string& clk = "clk",
                   const std::string& rst = "rst");
  void ExportIla(const InstrLvlAbsPtr& ila_ptr_);
  void ExportTopLevelInstr(const InstrPtr& instr_ptr_);
}; // class VerilogGenerator

}; // namespace ilang

#endif // ILANG_VERILOG_OUT_VERILOG_GEN_H__