verilog_analysis.h

// ---Hongce Zhang

#ifndef ILANG_VERILOG_IN_VERILOG_ANALYSIS_H__
#define ILANG_VERILOG_IN_VERILOG_ANALYSIS_H__

#include <map>

// I have to put this include here, because it needs to know the class
// VerilogAnalyzerBase
#include <ilang/verilog-in/verilog_analysis_wrapper.h>
#include <ilang/verilog-in/verilog_const_parser.h>

extern "C" {
#include <verilogparser/verilog_ast_util.h>
#include <verilogparser/verilog_parser.h>
}

namespace ilang {

class VerilogAnalyzer;

class SignalInfoPort : public SignalInfoBase {
protected:
  ast_port_declaration* _def;

public:
  SignalInfoPort(ast_port_declaration* def, const std::string& full_name,
                 VerilogAnalyzerBase::hierarchical_name_type tp,
                 const std::map<std::string, int>* const width_info,
                 const VerilogAnalyzer* _ana);
  ast_port_declaration* get_def() { return _def; }
}; // class SignalInfoPort

class SignalInfoReg : public SignalInfoBase {
protected:
  ast_reg_declaration* _def;

public:
  SignalInfoReg(ast_reg_declaration* def, const std::string& full_name,
                VerilogAnalyzerBase::hierarchical_name_type tp,
                const std::map<std::string, int>* const width_info,
                const VerilogAnalyzer* _ana);
  ast_reg_declaration* get_def() { return _def; }
}; // class SignalInfoPort

class SignalInfoWire : public SignalInfoBase {
protected:
  ast_net_declaration* _def;

public:
  SignalInfoWire(ast_net_declaration* def, const std::string& full_name,
                 VerilogAnalyzerBase::hierarchical_name_type tp,
                 const std::map<std::string, int>* const width_info,
                 const VerilogAnalyzer* _ana);
  ast_net_declaration* get_def() { return _def; }
}; // class SignalInfoPort

class VerilogAnalyzer : public VerilogAnalyzerBase {
public:
  using path_vec_t = VerilogAnalyzerBase::path_vec_t;
  using vlg_loc_t = VerilogAnalyzerBase::vlg_loc_t;
  typedef std::map<std::string, ast_module_declaration*> name_module_ast_map_t;
  using name_names_map_t = VerilogAnalyzerBase::name_names_map_t;
  using mod_inst_t = VerilogAnalyzerBase::mod_inst_t;
  using name_insts_map_t = VerilogAnalyzerBase::name_insts_map_t;
  using hierarchical_name_type = VerilogAnalyzerBase::hierarchical_name_type;
  using name_type_buffer_t = VerilogAnalyzerBase::name_type_buffer_t;
  using name_decl_buffer_t = VerilogAnalyzerBase::name_decl_buffer_t;
  using module_io_vec_t = VerilogAnalyzerBase::module_io_vec_t;
  typedef std::map<std::string, ast_module_instantiation*> mod_inst_ast_t;
  typedef std::map<std::string, mod_inst_ast_t> name_insts_ast_map_t;

protected:
  path_vec_t vlg_include_path;
  path_vec_t vlg_src_files;
  std::string top_module_name;
  name_module_ast_map_t name_module_map;
  name_names_map_t module_to_whereuses_map;
  name_insts_map_t modules_to_submodules_map;
  name_insts_ast_map_t modules_to_submodule_inst_ast_map;

  std::string top_inst_name;

public:
  // --------------------- CONSTRUCTOR ---------------------------- //
  VerilogAnalyzer(const path_vec_t& include_path, const path_vec_t& srcs,
                  const std::string& top_module_inst_name,
                  const std::string& optional_top_module);

  // --------------------- DESTRUCTOR ---------------------------- //
  ~VerilogAnalyzer();

protected:
  // --------------------- HELPER FUNCTIONS ---------------------------- //
  void invoke_parser();
  void find_top_module(verilog_source_tree* source,
                       const std::string& optional_top_module);
  void check_resolve_modules(verilog_source_tree* source);
  void create_module_submodule_map(verilog_source_tree* source);
  static unsigned instance_count;

public:
  // --------------------- MEMBERS ---------------------------- //
  hierarchical_name_type
  check_hierarchical_name_type(const std::string& net_name) const;
  vlg_loc_t find_definition_of_signal(const std::string& net_name) const;
  vlg_loc_t find_definition_of_a_module(const std::string& module_name) const;
  void* find_declaration_of_name(const std::string& net_name) const;
  vlg_loc_t name2loc(const std::string& net_name) const;
  vlg_loc_t get_module_inst_loc(const std::string& inst_name) const;
  std::string get_top_module_name() const { return top_module_name; }
  module_io_vec_t get_top_module_io(
      const std::map<std::string, int>* const width_info = NULL) const;
  SignalInfoBase
  get_signal(const std::string& net_name,
             const std::map<std::string, int>* const width_info = NULL) const;
  vlg_loc_t get_endmodule_loc(const std::string& inst_name) const;
  std::string get_module_name_of_net_name(const std::string& net_name) const;

  // --------------------- HELPERS ---------------------------- //
  static std::ostream& PrintMeta(std::ostream& os, const ast_metadata& md) {
    return (os << (md.file) << ":" << (md.line));
  }
  template <class T>
  static std::ostream& PrintMetaAst(std::ostream& os, const T* n) {
    return PrintMeta(os, n->meta);
  }
  static vlg_loc_t Meta2Loc(const ast_metadata& md) {
    return vlg_loc_t(md.file, md.line);
  }
  // --------------------- FOR verilog const parser ----------- //
  bool get_hierarchy_from_full_name(
      const std::string& full_name,
      VerilogConstantExprEval::param_def_hierarchy& hier,
      ast_module_declaration** lowest_level) const;

private:
  // --------------------- MEMBERS ---------------------------- //
  mutable name_type_buffer_t name_type_buffer;
  mutable name_decl_buffer_t name_decl_buffer;
  hierarchical_name_type
  _check_hierarchical_name_type(const std::string& net_name) const;

public:
  bool in_bad_state() const { return _bad_state; }

private:
  bool _bad_state;
  bool _bad_state_return() const;

}; // class VerilogAnalyzer

}; // namespace ilang

#endif // ILANG_VERILOG_IN_VERILOG_ANALYSIS_H__