directive.h

// --- Hongce Zhang
#ifndef ILANG_VTARGET_OUT_DIRECTIVE_H__
#define ILANG_VTARGET_OUT_DIRECTIVE_H__

#include <functional>
#include <map>
#include <string>
#include <tuple>

#include <ilang/verilog-in/verilog_analysis_wrapper.h>
#include <ilang/verilog-out/verilog_gen.h>
#include <ilang/vtarget-out/absmem.h>

namespace ilang {

/*
**CLOCK**
**RESET**
**KEEP**
**NC**
**MEM** rdata/raddr/ren/wdata/waddr/wen.?
*/
class IntefaceDirectiveRecorder {
public:
  typedef enum {
    KEEP = 0,
    NC /*not connected*/,
    SO /*state out*/,
    INPUT /*general input*/,
    RESET,
    CLOCK,
    MEM_R_A,
    MEM_R_D,
    MEM_R_EN,
    MEM_W_A,
    MEM_W_D,
    MEM_W_EN,
    START
  } inf_dir_t;
  typedef std::pair<inf_dir_t, std::string> inf_connector_t;
  typedef std::map<std::string, inf_connector_t> mod_inst_rec_t;
  using vlg_sig_t = VerilogGeneratorBase::vlg_sig_t;
  using vlg_sig_vec_t = VerilogGeneratorBase::vlg_sigs_t;
  typedef std::function<bool(const std::string&, const SignalInfoBase&)>
      ila_input_checker_t;
  typedef std::function<std::pair<unsigned, unsigned>(const std::string&)>
      ila_mem_checker_t;
  typedef std::function<void(const std::string&)> assmpt_inserter_t;
  using rport_t = VerilogGeneratorBase::rport_t;
  using wport_t = VerilogGeneratorBase::wport_t;

public:
  static bool beginsWith(const std::string& c, const std::string& s);
  static bool isSpecialInputDir(const std::string& c);
  static bool isSpecialInputDirCompatibleWith(const std::string& c,
                                              const SignalInfoBase& vlg_sig);
  // static bool interfaceDeclareTop(const std::string & c);
  // --- more to added
  // -------------------- CONSTRUCTOR ---------------------------- //
  IntefaceDirectiveRecorder(bool reset_vlg) : _reset_vlg(reset_vlg) {}

  // ------------------------ MEMBERS ------------------------ //
  void Clear(bool reset_vlg);
  std::string GetVlgModInstString(VerilogGeneratorBase& gen) const;
  void VlgAddTopInteface(VerilogGeneratorBase& gen) const;
  void RegisterInterface(const SignalInfoBase& vlg_sig,
                         const std::string& refstr, ila_input_checker_t chk,
                         ila_mem_checker_t mget);
  void RegisterExtraWire(const std::string& io_name,
                         const std::string& outside_name);
  std::string ConnectMemory(const std::string& directive,
                            const std::string& ila_state_name,
                            const std::map<unsigned, rport_t>& rports,
                            const std::map<unsigned, wport_t>& wports,
                            int ila_addr_width, int ila_data_width,
                            bool abs_read);
  void InsertAbsMemAssmpt(assmpt_inserter_t inserter);

  void SetMemName(const std::string& directive,
                  const std::string& ila_state_name, bool abs_read);

  void SetMemNameAndWidth(const std::string& directive,
                          const std::string& ila_state_name, bool abs_read, int,
                          int);

  std::string GetAbsMemInstString(VerilogGeneratorBase& gen,
                                  const std::string& endCond);
  std::pair<std::string, unsigned int>
  KeepMemoryPorts(const std::string& mem_name, const std::string& port_name,
                  bool caller_build_wire);

protected:
  void ModuleInstSanityCheck(VerilogGeneratorBase& gen) const;
  void ConnectModuleInputAddWire(const std::string& short_name, unsigned width);
  void ConnectModuleOutputAddWire(const std::string& short_name,
                                  unsigned width);

protected:
  mod_inst_rec_t mod_inst_rec;
  // a wire will not appear in two or more of the category
  vlg_sig_vec_t input_wires;
  vlg_sig_vec_t output_wires;
  vlg_sig_vec_t internal_wires;
  std::map<std::string, VlgAbsMem> abs_mems;
  bool _reset_vlg;

}; // class IntefaceDirectiveRecorder

/*
**MEM**.?
*/

class StateMappingDirectiveRecorder {
public:
  // ------------------------------ HELPER
  // ------------------------------------//
  static bool isSpecialStateDir(const std::string& c);
  static bool isSpecialStateDirMem(const std::string& c);
  static bool isSpecialUnknownFunctionName(const std::string &funcname);
  static bool isSpecialUnknownFunction(const FuncPtr &func_ptr);
}; // class StateMappingDirectiveRecorder

}; // namespace ilang

#endif // ILANG_VTARGET_OUT_DIRECTIVE_H__