Here is a list of all documented class members with links to the class documentation for each member:

- i -

• I2JSer() : ilang::I2JSer
• I2JSerPtr : ilang::I2JSer
• id() : ilang::Symbol
• idCounter : ilang::VerilogGeneratorBase
• IExprVec : ilang::Unroller
• Ila() : ilang::Ila
• ila() : ilang::RefinementMap
• Ila() : ilang::Ila
• ila_file_name : ilang::VlgSglTgtGen
• ila_func_app : ilang::VerilogGeneratorBase
• ila_input_checker_t : ilang::IntefaceDirectiveRecorder
• ila_map_name : ilang::VlgAbsMem
• ila_mem_checker_t : ilang::IntefaceDirectiveRecorder
• ila_rports : ilang::VerilogGeneratorBase , ilang::VlgAbsMem
• ila_wports : ilang::VerilogGeneratorBase , ilang::VlgAbsMem
• IlaBoolValType : ilang::VerilogGeneratorBase
• IlaBvValType : ilang::VerilogGeneratorBase
• IlaBvValUnsignedType : ilang::VerilogGeneratorBase
• IlaGetInput() : ilang::VlgSglTgtGen
• IlaGetState() : ilang::VlgSglTgtGen
• ILANameStateNameSetMap : ilang::InterIlaUnroller , ilang::MemoryModel
• IlaPtrVec : ilang::InterIlaUnroller
• IlaSim() : ilang::IlaSim
• Ilator() : ilang::Ilator
• IlaZ3Unroller() : ilang::IlaZ3Unroller
• ImportFromFile() : ilang::InvariantObject
• in_bad_state() : ilang::VerilogAnalyzer , ilang::VerilogInfo , ilang::VerilogVerificationTargetGenerator , ilang::VlgSglTgtGen , ilang::VlgVerifTgtGen , ilang::smt::SmtlibInvariantParser
• IncEqCheck() : ilang::CommDiag
• inf_connector_t : ilang::IntefaceDirectiveRecorder
• inf_dir_t : ilang::IntefaceDirectiveRecorder
• info_t : ilang::VerilogModifier , ilang::VlgSglTgtGen_Yosys
• init() : ilang::InstrLvlAbs , ilang::Ila
• init_assumpts : ilang::VerilogGeneratorBase
• init_num() : ilang::InstrLvlAbs , ilang::Ila
• init_shared_vars_z3_ : ilang::InterIlaUnroller
• init_stmts : ilang::VerilogGeneratorBase
• InitSize() : ilang::MemoryModel
• input() : ilang::InstrLvlAbs , ilang::Ila
• input_num() : ilang::InstrLvlAbs , ilang::Ila
• input_wires : ilang::IntefaceDirectiveRecorder
• inputs : ilang::VerilogGeneratorBase
• insert() : ilang::MapSet< Key, T >
• InsertAbsMemAssmpt() : ilang::IntefaceDirectiveRecorder
• InsertFromAnotherInvObj() : ilang::InvariantObject
• inst() : ilang::TraceStep
• instance_count : ilang::VerilogAnalyzer
• instr() : ilang::InstrLvlAbs , ilang::InstrTranNode , ilang::Ila
• Instr() : ilang::Instr
• instr_num() : ilang::InstrLvlAbs , ilang::Ila
• InstrCnstPtr : ilang::Instr
• InstrLvlAbs() : ilang::InstrLvlAbs
• InstrLvlAbsCnstPtr : ilang::InstrLvlAbs
• InstrLvlAbsMap : ilang::InstrLvlAbs
• InstrLvlAbsPtr : ilang::Ast , ilang::InstrLvlAbs
• InstrPtr : ilang::Instr
• InstrRef() : ilang::InstrRef
• InstrSeq() : ilang::InstrSeq
• InstrSeqPtr : ilang::InstrSeq
• InstrTranEdge() : ilang::InstrTranEdge
• InstrTranNode() : ilang::InstrTranNode
• InstructionNoReset : ilang::VlgVerifTgtGenBase::_vtg_config
• InstrVec : ilang::PathUnroll , ilang::InterIlaUnroller , ilang::MemoryModel
• IntefaceDirectiveRecorder : ilang::VerilogGeneratorBase , ilang::IntefaceDirectiveRecorder
• InterIlaUnroller() : ilang::InterIlaUnroller
• internal_name : ilang::smt::state_var_t
• internal_wires : ilang::IntefaceDirectiveRecorder
• inv() : ilang::RefinementMap
• inv_extra_free_vars : ilang::InvariantObject
• inv_extra_vlg_vars : ilang::InvariantObject
• inv_num() : ilang::RefinementMap
• inv_parser : ilang::smt::smtlib2_abstract_parser_wrapper
• inv_pred_name : ilang::smt::SmtlibInvariantParser
• inv_vec_t : ilang::InvariantObject
• inv_vlg_exprs : ilang::InvariantObject
• InvariantCheckKeepMemory : ilang::VlgVerifTgtGenBase::_vtg_config
• InvariantObject() : ilang::InvariantObject
• InvariantSynthesisKeepMemory : ilang::VlgVerifTgtGenBase::_vtg_config
• InvariantSynthesisReachableCheckKeepOldInvariant : ilang::VlgVerifTgtGenBase::_vtg_config
• invoke_parser() : ilang::VerilogAnalyzer
• is_ast() : ilang::Ast , ilang::Object
• is_bad_signal() : ilang::SignalInfoBase
• is_bool() : ilang::smt::var_type , ilang::Sort , ilang::SortBool , ilang::Expr
• is_bv() : ilang::smt::var_type , ilang::SortBv , ilang::Expr , ilang::Sort
• is_const() : ilang::ExprConst , ilang::Expr
• is_datatype() : ilang::smt::var_type
• is_expr() : ilang::Ast , ilang::Expr
• is_facet_tracestep() : ilang::TraceStep
• is_final_tracestep() : ilang::TraceStep
• is_func() : ilang::Ast
• is_init_tracestep() : ilang::TraceStep
• is_input() : ilang::VerilogAnalyzerBase , ilang::SignalInfoBase
• is_instr() : ilang::Object , ilang::Instr
• is_instr_lvl_abs() : ilang::InstrLvlAbs , ilang::Object
• is_io_sig() : ilang::SignalInfoBase , ilang::VerilogAnalyzerBase
• is_mem() : ilang::Expr , ilang::SortMem , ilang::Sort
• is_module() : ilang::VerilogAnalyzerBase
• is_op() : ilang::Expr , ilang::ExprOp
• is_output() : ilang::VerilogAnalyzerBase , ilang::SignalInfoBase
• is_reg() : ilang::VerilogAnalyzerBase , ilang::SignalInfoBase
• is_reg_t : ilang::CexExtractor
• is_spec() : ilang::InstrLvlAbs
• is_state_name() : ilang::smt::YosysSmtParser
• is_var() : ilang::ExprVar , ilang::Expr
• is_wire() : ilang::VerilogAnalyzerBase
• isSpecialInputDir() : ilang::IntefaceDirectiveRecorder
• isSpecialInputDirCompatibleWith() : ilang::IntefaceDirectiveRecorder
• isSpecialStateDir() : ilang::StateMappingDirectiveRecorder
• isSpecialStateDirMem() : ilang::StateMappingDirectiveRecorder
• isSpecialUnknownFunction() : ilang::StateMappingDirectiveRecorder
• isSpecialUnknownFunctionName() : ilang::StateMappingDirectiveRecorder
• isValidVerifBackend() : ilang::VlgVerifTgtGenBase
• ite_stmts : ilang::VerilogGeneratorBase
• ItEdgePtr : ilang::InstrTranEdge
• items : ilang::smt::smt_file
• IteUnknownAutoIgnore : ilang::VlgVerifTgtGenBase::_vtg_config
• ItNodePtr : ilang::InstrTranNode